Rodrigo Possamai Bastos

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS

Bulk Built-In Current Sensors (bbicss) were introduced to detect the anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. To date, the experimental testing of only one bbics architecture was reported in the scientific bibliography. It reports an unexpected weakness in its ability to monitor nmos transistors. Based on experimental measures, we propose an explanation of this weakness and also the use of triple-well cmos to offset it. Further, we introduce a new bbics architecture well suited for triple-well that offers high detection sensitivity and low area overhead.

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection

Bulk Built-In Current Sensors (BBICSs) are able to detect anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. This paper presents a new strategy to design BBICSs with optimal transient-fault detection sensitivity while keeping low both area and power overheads. The approach allows increasing the detection sensitivity by setting an asymmetry in the flipping ability of the sensors latch. In addition, we introduce a mechanism to tune the delay of the bulk access transistors that improves even more the BBICS detection sensitivity. The proposed design strategy offers a good compromise between fault detection sensitivity and power consumption; moreover it makes feasible the use of several CMOS processes.

Comparison of bulk built-in current sensors in terms of transient-fault detection sensitivity

Several architectures of Bulk Built-In Current Sensors (BBICS) were recently proposed to monitor transient faults induced on integrated circuits by radiation or malicious sources. This work compares for the first time all existing static BBICS architectures in terms of their sensitivities to detect transient faults. In addition, we propose a new static BBICS that presents better results of transient-fault detection sensitivity than previous sensor architectures.

Simple tri-state logic Trojans able to upset properties of ring oscillators

Inserting hardware Trojans (HT) in ring oscillators (RO) of integrated systems is a malicious method that can considerably modify the behaviour of system circuits to produce undesired operations. This work presents and demonstrates three still unknown types of transistor-level Trojans based on the classic tri-state logic. If triggered, the presented HT are able to substantially change the jitter and frequency of RO. If disabled, thanks to their tri-state logic and tiny sizes, the circuit behaviour is not significant modified, making the Trojan detection through conventional functional testing or side-channel analysis unlikely. Results show the typical frequency of a 7-stage RO in CMOS 65-nm technology is kept within process corners if HT is off, and it is decreased by a factor of up to 0.7 when HT is on.

High-level synthesis for event-based systems

This paper envisions a design flow for empowering designers in the fast development of low-power event-driven processing chains. This flow takes advantage of level-crossing sampling schemes and asynchronous circuitry. Event-driven paradigm allows better-than-worst-case performance during periods of high-activity of the captured signal as well as a natural stand-by during low-activity periods. The proposed flow uses the specific knowledge of the targeted application and its signals, and a high-level description of the processing algorithm to synthesize a dedicated analog-to-digital converter, which performs the level-crossing sampling, and a digital signal processing unit. The latter is synthesized thanks to a high-level synthesis algorithm following a control/datapath decomposition style. The asynchronous control part is based on distributed asynchronous controllers while the datapath remains similar to a synchronous datapath.

Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology

Reducing voltage is a traditional strategy for designing and activating low-power mode of integrated systems. Low voltages otherwise make slower components that can cause critical timing violations in synchronous circuits. On the contrary, asynchronous circuits, which have no clock constraints, are capable to adapt to delay variations. This paper presents the minimum operation voltages of the fundamental asynchronous components, the C-elements, on recent FD-SOI 28-nm technology. Results show that conventional scheme of the C-element can reduce power by a factor of 34 for the less consuming scheme if operating at minimum voltage of 0.28 V instead of nominal 1.00 V. In addition, a low-voltage conventional C-element on FD-SOI 28-nm with RVT transistor consumes about one-third of the power of its counterpart on bulk 65-nm CMOS technology.

Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits

Abstract Todays integrated circuits are liable to operate under transient faults created either by radiation or malicious sources of perturbation. Among the many techniques for the detection of transient faults, Bulk Built-In Current Sensors (BBICS) present attractive low-cost and efficient features for the protection of circuits. This article provides a survey of published BBICS architectures and compares them with regard to their sensitivities in detecting transient faults. Moreover, a new dynamic BBICS architecture is introduced with improved detection sensitivity, negligible power consumption, and reduced area overhead.

Importance of IR drops on the modeling of laser-induced transient faults

Laser fault injection attacks induce transient faults by locally generating transient currents capable of temporarily flip the outputs of several gates. Many models used to simulate transient faults induced by laser consider several elements to better represent the effects of the laser on ICs. However, a laser-induced current between VDD and GND, which provokes significant IR drops, has been neglected. This paper highlights the importance of the induced IR drops on the modeling of laser-induced transient faults by using IR drop CAD tools. It also shows that laser-induced IR drops can be sufficiently strong to produce alone transient faults. As a result, the number of faults on a case-study circuit is accentuated whether IR drop effects are taken into account.

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines

Asynchronous circuits are interesting alternatives for implementing ultra-low power systems but they are more challenging to design. This work provides methods for designers to specify, verify, and implement self-timed pipelines. The connection of standard primitives allows specifying a control circuit. A method to derive a Petri net based model of this circuit is presented. The modeled transactions are only those necessary at a high level for the circuit verification and performance analysis. Additionally, the proposed framework includes merge and split choice structures in the control circuit for further reducing the power consumption of the targeted systems. It is associated with a design flow which uses standard EDA tools. The paper presents two practical examples illustrating how this framework can be used to design low-power systems based on a datapath specification: a finite impulse response (FIR) filter and an advanced encryption standard (AES) cipher. The obtained asynchronous FIR is 20% smaller and consumes 30% less energy compared to the synchronous design. The obtained asynchronous AES is 2% larger but consumes three times less energy than its synchronous counterpart.

Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors

The mass production of secure circuits demands nowadays new testing methods able to detect the possible existence of hardware Trojans, which might be even a slight layout alteration. This paper proposes a new method for the detection of Trojans by exploiting preexisting current sensors that are originally built in systems subcircuits as online-testing devices for detecting radiation- or laser-induced transient currents. In the proposed method, the sensor operates as an offline-testing mechanism to provide digital signatures of the subcircuits substrate after injection of current pulses into MOSFET body terminals. Simulation results considering process variations demonstrate the effectiveness of the method on detecting gate- and layout-level Trojans.