Jeffrey A. Fredenburg

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm2. Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management

Although closed-loop deep brain stimulation (DBS) promises treatment of many neurological disorders, an implantable system-on-chip (SoC) implementing an effective closed-loop DBS algorithm has not been demonstrated. This work introduces a logarithmic, closed-loop DBS system that detects and processes low-frequency brain field signals to control and adapt stimulation currents. The system records and processes neural signals with four low-noise neural amplifier (LNA) channels, a multiplexed logarithmic ADC, and two high-pass and two low-pass digital logarithmic filters. Logarithmic processing saves power and achieves high dynamic range. A logarithmic domain digital signal processor (DSP) and PI-controller controls eight current stimulator channels and enables closed-loop stimulation. An RF transceiver, a clock generator, and a power harvester are also included in the system to achieve a complete implantable SoC. The 4 mm2 180 nm CMOS prototype consumes a total of 468 μW for recording and processing neural signals, for stimulation, and for two-way wireless communication.

Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch

Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations.

A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders

A log-based closed-loop Deep Brain Stimulation system detects and processes low-frequency brain field signals to optimize stimulation parameters. The fully self-contained single-chip system incorporates LNAs, a log-ADC, digital log-filters, a log-DSP with a PI-controller, current stimulators, a two-way wireless transceiver, a clock generator, and an RF energy harvester. The 2×2mm2 180nm CMOS prototype consumes 468μW for recording and processing neural signals, stimulation, and for two-way wireless communication.

An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS

A circuit technique for directly interfacing with 120 V AC mains in conventional CMOS is presented. An on-chip capacitive divider steps-down the 120 V AC supply, which is then regulated. The approach makes use of the very high breakdown voltage of the dielectric between interconnect layers in conventional CMOS technology. This fully integrated scheme is orders of magnitude smaller than traditional approaches. A prototype circuit is fabricated in 130 nm CMOS and converts 120 V AC to a 3.5 V DC supply.

A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression

This work presents a bidirectional neural interface circuit that enables simultaneous recording and stimulation with a stimulation artifact cancellation circuit. The system employs a common average referencing (CAR) front-end circuit to suppress cross-channel environmental noise to further facilitate use in clinical environment. This paper also introduces a new range-adapting (RA) SAR ADC to lower the system power consumption. A prototype is fabricated in 0.18 μm CMOS and characterized and tested in vivo in an epileptic rat model. The prototype attenuates stimulation artifacts by up to 42 dB and suppresses cross-channel noise by up to 39.8 dB. The measured power consumption per channel is 330 nW, while the area per channel is 0.17 mm2.

An N-path filter enhanced low phase noise ring VCO

A novel self-filtering scheme breaks the typical tradeoff between noise and power, enabling a ring oscillator to approach the phase noise performance of an LC oscillator. The prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) achieves a measured phase noise of -110dBc/Hz at a 1MHz offset frequency for an oscillation frequency of 1.0GHz. The self-clocked N-path filter reduces the phase noise by 10dB and 28dB for 1.0GHz and 300MHz oscillation frequencies, respectively. Implemented in 65nm CMOS, the NPFRVCO occupies a die area of 0.015 mm2 and consumes 4.7mW from 1.2V power supply when operating at 1.0GHz. The NPFRVCO has a measured frequency tuning range from 300MHz to 1.6GHz and achieves a FoM of 163dB at 1MHz offset.

Ultra low power microsystems using RF energy scavenging (invited)

RF energy scavenging enable very small, battery-less sensing and processing systems. Power and timing information are extracted from an RF signal from a base station. A single chip RF powered system can include digital processing, two way telemetry and complete sensor interfaces.

A 16-channel noise-shaping machine learning analog-digital interface

A 16-channel machine learning digitizing interface embeds Inner-Product calculation within a Delta-Sigma Modulator (IPDSM) array canceling quantization noise and noise shaping the multiplicand. The prototype, with 16 independent IPDSM channels occupies a core area of 0.95mm2 in 65 nm CMOS. Each channel performs up to 100M multiplications/s. The system is demonstrated with a standard machine learning scheme for image recognition. It achieves the same classification accuracy for the MNIST set of hand-written digits as with the same algorithm on floating point DSP.

Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression

We present the first bi-directional neural interface chip that employs a stimulation artifact cancellation circuit to allow concurrent recording and stimulation. In order to further suppress cross-channel common-mode noise, we incorporated a novel common average referencing (CAR) circuit in conjunction with range-adapting (RA) SAR ADC for low-power implementation. The fabricated prototype attenuates stimulation artifacts by up to 42 dB and suppresses common noise among channels by up to 39.8 dB at 330 nW and in an area of 0.17 mm2 per channel.