Michael P. Flynn

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0/spl deg/C to 85/spl deg/C. The circuits were fabricated on a generic 0.5-/spl mu/m digital CMOS process.

A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-

Super-regeneration is re-examined for its simplicity and power efficiency for low-power, short-range communication. A fully integrated super-regenerative receiver in 0.13-mum CMOS is designed to operate in the 2.4 GHz ISM band. A frequency synthesizer scheme tunes the passband. Successive approximation register (SAR) logic driving a current digital-to-analog converter (DAC) calibrates the quench signal to enhance the selectivity of a Q-enhanced filter and the sensitivity of super-regeneration. A single-chip prototype receiver occupies less than 1 mm2, has a turn-on time of 83.6 mus, a channel spacing of 10 MHz, and a sensitivity of -90 dBm. A data rate of 500 kb/s is achieved with a power consumption of 2.8 mW, corresponding to energy consumption of 5.6 nJ per received bit.

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We present a new architecture for wireless power and data telemetry that recovers power and a system clock from a weak incident RF signal. A high-efficiency RF-DC converter generates a 3-VDC supply for the system from a -12.3-dBm incident RF signal, gathered by a commercial 50-/spl Omega/ antenna. A system clock is extracted from the same incident signal, by an injection-locked LC oscillator. Sub-harmonic injection-locking facilitates the separation of the incident and the transmit signal frequencies, without need for a PLL. The proposed architecture is used in a long-range telemetry device, incorporating an on-chip ADC, and employing active telemetry for data transmission. Data is transmitted through binary phase-shift-keying of a 900-MHz carrier. The prototype, implemented in 0.25-/spl mu/m CMOS, occupies less than 1 mm/sup 2/. A wireless operation range of more than 18 meters is indicated by anechoic chamber testing.

CMOS

This paper describes a neurostimulation IC for use in advanced closed-loop neurostimulation applications, such as deep brain stimulation (DBS) for treatment and research of neurological disorders including Parkinsons disease. This system senses and filters neural activity with eight pre-amplifiers, a 200 kS/s 8-bit log ADC and digital filters and incorporates 64 programmable current-stimulation channels. The entire device, implemented in 0.18 μm CMOS, occupies 2.7 mm2 and consumes 89 μW in normal operation mode and 271 μW in configuration mode from a 1.8 V supply.

A new transponder architecture with on-chip ADC for long-range telemetry applications

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10-11 at 4 GS/s.

A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm2. Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.

A 4-GS/s 4-bit Flash ADC in 0.18-

As feature size and supply voltage shrink, digital calibration incorporating redundancy of flash analog-to-digital converters is becoming attractive. This new scheme allows accuracy to be achieved through the use of redundancy and reassignment, effectively decoupling analog performance from component matching. Very large comparator offsets (several LSBs) are tolerated, allowing the comparators to be small, fast and power efficient. In this paper, we analyze this scheme and compare with it with more traditional approaches.

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Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirement, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25~ digital CMOS process occupies 1.2mm2 and dissipates llOmW from a 2.2V supply at 300Ms/s.

CMOS

This work presents a compact, low-power, time-based architecture for nanometer-scale CMOS analog-to-digital conversion. A pulse position modulation ADC architecture is proposed and a prototype 9 bit PPM ADC incorporating a two-step TDC scheme is presented as proof of concept. The 0.06 mm2 prototype is implemented in 90 nm CMOS and achieves 7.9 effective bits across the entire input bandwidth and dissipates 14 μW at 1 MS/s.

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

A CMOS multi-level (8-PAM) transceiver is described. Preemphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The device transmits at up to 1.3Gb/s and has a measured BER of for an 81OMb/s PRBS transmission. The device, packaged in a 68 pin CLCC, is implemented k 0.5pm digital CMOS, occupies 2”’ and dissipates 400mW from a 3.3V supply.