Jeffrey C. Stevens

Computer system with adaptive memory arbitration scheme

Computer fan speed system to reduce audible perceptibility of fan speed changes

Computer system employing memory controller and bridge interface permitting concurrent operation

Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus

Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation

Programmable memory controller having two level look-up for memory timing parameter

Method of supporting audio for KVM extension in a server platform

Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus

POWER CONSUMPTION LIMIT ASSOCIATED WITH POWER OVER ETHERNET (POE) COMPUTING SYSTEM

Solution for integrating a KVM extension transmitter with a graphics controller on an add-in card