Jeffrey R. Brown

Apparatus including memory system controllers and related methods

Apparatus for performing a low latency memory read with concurrent snoop

Verification of port list integrity in a hardware description language file

Low latency memory read with concurrent pipe lined snoops

Inserting buffers between modules to limit changes to inter-module signals during ASIC design and synthesis

Inter-module buffer determination methodology for ASIC synthesis

Apparatus for supporting multiple delayed read transactions between computer buses

Apparatus including memory channel control circuit and related methods for relaying commands to logical units

Method for supporting multiple delayed read transactions between computer buses

Inter-module data management methodology for circuit synthesis