Joseph M. Jeddeloh

System and method for selective memory module power management

Memory hub with internal cache and/or memory access prediction

Memory controller with low skew control signal

Timing circuit for high speed memory

System and method for self-testing and repair of memory modules

System and method for remapping defective memory locations

System and method for on-board diagnostics of memory modules

DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE

Multiple processor system and method including multiple memory hub modules

Method of processing memory requests in a pipelined memory controller