Jeffrey R. DeBord

Yield Learning and Process Optimization on 65-nm CMOS Technology Accelerated by the Use of Short Flow Test Die

Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation and gate and premetal dielectric/contact loops of a 65-nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.

Failure Mode Detection and Process Optimization for 65 nm CMOS Technology

Short loop test flows have been commonly used in back end of line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation (STI), gate and pre- metal dielectric (PMD)Z contact loops of a 65 nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.

0.50-μm pitch metal integration in 0.18-μm technology

As metal pitch requirements for 0.18 micrometer generation logic shrink to 0.50 micrometer pitch and below, the capability of 248 nm deep ultraviolet (DUV) lithography is challenged, especially for isolated narrow lines. Standard illumination methods and binary masks do not give acceptable performance on both dense and isolated 0.25 micrometer structures simultaneously. Two methods available to reliably pattern isolated structures with enough depth of focus (DOF) for high volume manufacturing are Optical Proximity Correction (OPC) techniques such as scattering bars and serifs or the addition of a selective size adjust that sizes all isolated narrow leads up to a width with acceptable DOF. The present work will discuss a manufacturable 0.50 micrometer pitch metallization scheme for leading edge logic applications incorporating DUV lithography, an inorganic silicon oxy- nitride (SION) anti-reflective coating (ARC) layer and standard etch chemistries, with a comparison of the performance of scattering bars and selective size adjusts on isolated lines. Results were characterized by SEM cross sections and electrical data extracted from parametric test structures. Also discussed will be a general methodology of implementing elements of OPC with an eye towards robustness, manufacturability and simplicity of implementation.