Ashesh Parikh

Impact of context dependenent variability in CMOS embedded with SiGe on circuit performance & power

For CMOS circuits, the increase in power consumption has been curtailed in recent years by introducing mechanical stress to achieve device speed gain over and above the traditional speed vs. power tradeoffs achieved only by scaling gate lengths. Starting with the 90nm silicon node, induced compressive stress by embedded SiGe is being used to increase the hole mobility in PMOS. Because of the context dependence of this stress, local variability of the device parameters is expected to increase with this process method. In this paper, we discuss a method of direct measurement of the channel stress using Synchrotron X-ray diffraction and show the impact of resulting increased mobility and increased local variation on the circuit performance using Monte Carlo SPICE simulations of CMOS invertor based as well as NAND based ring oscillators. Simulation results demonstrate how lower supply voltage can be used to meet performance targets with lower power consumption.

Simultaneous calibration of acid diffusion and developer loading parameters for computational lithography

Resist parameters for computational lithography model were extracted from a set of gratings. The gratings comprised of lines and spaces where the main feature proximity was modulated by placement of sub and near resolution assist features. Modulating the size of the assist features resulted in simultaneous variation of the amount of photo-acid and developer loading. The straight Gaussian kernel was modified to represent the effect of base quencher to the photo-acid. An additional density based kernel was created to represent the effect of developer loading. These kernels allowed for significant improvement in fitting error. The models were validated against an independent data-set comprised of asymmetric features.

Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.

Fast and accurate calibration for OPC process-window model using inverse weight algorithm

A data-set comprising of lines and spaces was collected by inline scanning electron microscope at a single measurement threshold. Input data included measurements from features of several sizes at a range of pitch values as well as the entire Bossung curve for certain critical features. Models were calibrated with and without scaling of cost weight. Weights were scaled using inverse weight algorithm based on the differential sensitivity to focus for various feature types to a given lithography system. The imaging and the resist empirical parameters were extracted by regression over the entire data-set and a truncated version of the same data-set. The through-focus fitting error reduced by over 50% from +/- 5% to 2% with the cost weights scaled using the inverse weight algorithm. The quickness combined with the ability to extract fitting parameters precisely using this technique has enabled implementation on various digital and analog layers ranging from 180nm to 65nm nodes.

Optimizing gate reticle to silicon flow for variability in low power circuits

Ultra-low-power circuits for applications such as biomedical implants and environmental monitoring are being designed to operate in the subthreshold regime. CMOS circuits in this regime are extremely susceptible to manufacturing process variations due to the exponential relationship of transistor sub-threshold drive current (Id) with threshold voltage (Vt) variation. In this paper, we explore the behavior of an inverter ring oscillator that was manufactured using 130nm process technology and operated at low supply voltage (Vdd). We then explore the effects of variations induced due to different aspects of the manufacturing process. Finally, we define the box of safe operation using an existing 130nm CMOS process and the required precision to achieve high yields by optimizing the gate reticle to silicon (Si) flow for the same.