Jeffrey R. LaRoche

High Performance Mixed Signal and RF Circuits Enabled by the Direct Monolithic Heterogeneous Integration of GaN HEMTs and Si CMOS on a Silicon Substrate

In this work we present recent results on the direct heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate. GaN HEMTs whose DC and RF performance are comparable to GaN HEMTs on SiC substrates have been achieved. As a demonstration vehicle we designed and fabricated a GaN amplifier with pMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects. This simple demonstration circuit is a building block for more advanced RF, mixed signal and power conditioning circuits, such as reconfigurable or linearized PAs with in-situ adaptive bias control, high power digital-to-analog converters (DACs), driver stages for on-wafer optoelectronics, and on-chip power distribution networks.

Annealing temperature dependence of contact resistance and stablity for Ti/Al/Pt/Au ohmic contacts to bulk n-ZnO

E-beam deposited Ti/Al/Pt/Au contacts on undoped (n∼1017 cm−3) bulk ZnO showed minimum specific contact resistance, ρc, of ∼6×10−4 Ω cm2 after annealing at 250 °C. This value was essentially independent of the surface cleaning procedure employed, including sequential solvent cleaning or H2 plasma exposure. Higher annealing temperatures degraded the ρc, and Auger electron spectroscopy depth profiling revealed increasing intermixing of the metal layers. The Al outdiffuses to the surface at temperatures as low as 350 °C, and the contact metallization is almost completely intermixed by 600 °C.

W-band metamorphic HEMT with 267 mW output power

This paper reports the highest W-band power output of metamorphic HEMT (MHEMT) technology to date. 267 mW single stage performances at 90 GHz are achieved on a 0.15 micron GaAs-based production line with improved manufacturability over InP HEMT. The single stage circuits presented here are building blocks for future MHEMT power amplifier development.

Increased Schottky barrier heights for Au on n- and p-type GaN using cryogenic metal deposition

An enhancement of ∼0.18eV (an 18% increase) in Schottky barrier height was obtained for Au deposited at cryogenic temperatures on n-type GaN relative to conventional deposition at 300K (barrier height of 1.0eV). Enhancements of 0.04–0.11eV were achieved for Au deposition on p-GaN under the same conditions. The increase in barrier height on n-GaN persists for annealing temperatures up to ∼200°C. At higher annealing temperatures, both types of diodes show a deterioration in rectifying behavior. The reverse current of low temperature deposited diodes was approximately two orders of magnitude lower than conventional Au∕n-GaN diodes. The ideality factor of the cryogenically processed n-type devices (∼1.06) was similar to that for room temperature diodes (1.13). This simple process method has potential for improving output resistance and power gain and lowering gate leakage current and noise in GaN-based transistors.

Thermal stability and etching characteristics of electron beam deposited SiO and SiO2

We have studied the thermal stability and etching characteristics of electron beam deposited SiO and SiO2. Scanning electron microscopy, Auger, atomic form microscopy, and ellipsometry were used to analyze the surface morphology, roughness, and film composition as a function of annealing temperatures. Both SiO and SiO2 showed excellent thermal stability up to 400 °C anneal and refractive index, surface morphology and pattern edge definition of both films barely changed. For higher temperature anneal, based on Auger analysis results, the ratio of Si/O of SiO2 film stayed constant after 700 °C. However, the Si/O ratio of SiO film increased from 0.54 to 0.62 due to oxygen outdiffusion. Dry etch characteristics of SiO and SiO2 were investigated using SF6 and NF3 discharges in a Plasma Therm inductively coupled plasma system. Wet etches were performed using buffered HF and HF/H2O solutions. Dry etch rates of SiO2 were comparable with that of conventional plasma enhanced chemical vapor deposition SiO2. SiO2 etc...

Improved Au Schottky contacts on GaAs using cryogenic metal deposition

The use of low temperatures (∼77K) during Au Schottky contact deposition onto n-GaAs produces an increase in barrier height from 0.73eV for room temperature diodes to 0.82eV. There is no evidence of drift in the forward current in either type of diode and the low temperature deposited samples show smoother Au layers and more abrupt Au∕GaAs interfaces as determined by x-ray reflectivity measurements. Both types of diodes show surface and bulk contributions to the reverse bias current. The diodes with Au deposited at cryogenic temperature did show higher ideality factors, which may result from contaminants gettered to the cold GaAs surface.

Device Processing for GaN High Power Electronics

Recent advances in developing process modules for GaN power devices are reviewed. These processes include damage removal in dry etched n- and p-GaN, implant doping and isolation, novel gate dielectrics, improved Schottky and ohmic contacts and deep via etching of SiC for hybrid GaN/SiC structures.

MBE growth of InP-HBT structures on Ge-on-insulator/Si substrates by MBE

MBE growth of InP-based HBTs on GeOI/Si substrates is described. A GaAs buffer is nucleated on the GeOI; then a graded InAlAs metamorphic buffer transitions the lattice constant to InP. TEM shows minimal anti-phase boundaries and limited dislocations propagating into the device layers. Large area DC parameters are similar to LM HBTs grown on InP. Small area devices exhibit peak current gain cutoff frequency (ft) of 170 GHz at 2 mA/mum2 nominal collector current density. Initial work involving selective epitaxial growth on patterned Ge substrates for future integration is also discussed.

Annealing temperature dependence of contact resistance and stability for Ti/Al/Pt/Au ohmic contacts to bulk n-ZnO

Summary form only given. The authors report on the annealing temperature dependence of contact resistance and morphology for Ti/Al/Pt/Au contacts on high-quality, undoped (n/spl sim/10/sup 17/ cm/sup -3/) bulk ZnO substrates. Two different surface cleaning procedures were employed, although it was found that in general the as-received surface produced the lowest specific contact resistances.