Jeffrey S. Walling

A Class-G Supply Modulator and Class-E PA in 130 nm CMOS

A class-G supply modulator utilizes parallel low- dropout (LDO) regulators that are controlled by comparators and negative feedback. It optimizes the power consumption of a nonlinear power amplifier (PA) operating with supply modulation, such that it draws current from one of multiple appropriately sized supply voltages as determined by the input signal envelope. The class-G modulator is used in conjunction with a class-E PA operating in an envelope elimination and restoration (EER) mode to efficiently amplify signals with large peak-to-average ratios. The measured maximum output power and power added efficiency (PAE) are 29.3 dBm and 69%, respectively. The class-G technique is demonstrated for a 64 QAM, OFDM input signal (symbol period = 4 mus) wherein the measured error vector magnitude (EVM) is 2.5% and the average efficiency of 22.6%.

A Switched-Capacitor RF Power Amplifier

A fully integrated switched-capacitor power amplifier (SCPA) utilizes switched-capacitor techniques in an EER/Polar architecture. It operates on the envelope of a nonconstant envelope modulated signal as an RF-DAC in order to amplify the signal efficiently. The measured maximum output power and PAE are 25.2 dBm and 45%, respectively. When amplifying an 802.11g 64-QAM orthogonal frequency-division multiplexing (OFDM) signal, the measured error vector magnitude is 2.6% and the average output power and power-added efficiencies are 17.7 dBm and 27%, respectively.

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to amplitude variations at its input. A modulator is introduced that takes outphased waveforms as its inputs and generates a pulse-width and pulse-position modulated (PWPM) signal as its output. The PWPM modulator is used in conjunction with a class-E PA to efficiently amplify constant envelope (e.g., GMSK) and non-constant envelope (e.g., QPSK, QAM, OFDM) signals with moderate peak-to-average ratios (PAR). The measured maximum output power of the PA is 28.6 dBm with a PAE of 28.5%, and the measured error vector magnitude (EVM) is 1.2% and 4.6% for GMSK and pi/4-DQPSK (PAR ap 4 dB) modulated signals, respectively.

A switched-capacitor power amplifier for EER/polar transmitters

Wireless high-speed communication standards such as WiFi, WiMax and LTE use spectrally-efficient OFDM modulation that encodes signal information in both amplitude and phase. Use of this non-constant envelope modulation requires a linear PA, operating at a less-than-peak signal level to realize higher linearity and inherently reduced efficiency. Because the PA is the dominant power consumer in most RF transceivers, operation with reduced efficiency leads to short battery lifetime and reduced mobility. Consequently, many efforts to utilize more efficient switching amplifiers with linearization circuitry have been made, notably through pulse-width modulation [1], outphasing [2] and envelope elimination and restoration (EER) [3,4]. Of the three, EER offers the best performance tradeoff between linearity, output power and efficiency; however, most previous implementations have come at the cost of large, power-hungry analog supply modulators. Additionally, conventional EER techniques are subject to nonlinearity induced by delay mismatch between the amplitude- and phase-modulated signal components. An alternative solution modulated the output power by selecting multiple PA unit cells [5], but this exhibits low efficiency at low output power levels because the power control is achieved by changing the total PA transconductance through switching of inefficient cells.

Distinguishing users with capacitive touch communication

As we are surrounded by an ever-larger variety of post-PC devices, the traditional methods for identifying and authenticating users have become cumbersome and time-consuming. In this paper, we present a capacitive communication method through which a device can recognize who is interacting with it. This method exploits the capacitive touchscreens, which are now used in laptops, phones, and tablets, as a signal receiver. The signal that identifies the user can be generated by a small transmitter embedded into a ring, watch, or other artifact carried on the human body. We explore two example system designs with a low-power continuous transmitter that communicates through the skin and a signet ring that needs to be touched to the screen. Experiments with our prototype transmitter and tablet receiver show that capacitive communication through a touchscreen is possible, even without hardware or firmware modifications on a receiver. This latter approach imposes severe limits on the data rate, but the rate is sufficient for differentiating users in multiplayer tablet games or parental control applications. Controlled experiments with a signal generator also indicate that future designs may be able to achieve datarates that are useful for providing less obtrusive authentication with similar assurance as PIN codes or swipe patterns commonly used on smartphones today.

Minimizing Energy Consumption in Body Sensor Networks via Convex Optimization

Body Sensor Networks (BSNs) consist of miniature sensors deployed on or implanted into the human body for health monitoring. Conserving the energy of these sensors, while guaranteeing a required level of performance, is a key challenge in BSNs. In terms of communication protocols, this translates to minimizing energy consumption while limiting the latency in data transfer. In this paper, we focus on polling-based communication protocols for BSNs, and address the problem of optimizing the polling schedule to achieve minimal energy consumption and latency. We show that this problem can be posed as a geometric program, which belongs to the class of convex optimization problems, solvable in polynomial time. We also introduce a dynamic priority vector for each sensor, based on the observation that relative priorities of sensors in a BSN change over time. This vector is used to develop a decision-tree based approach for resolving scheduling conflicts among devices. The proposed framework is applicable to a broad class of periodic polling-based communication protocols. We design one such protocol in detail and show that it achieves an improvement of approximately 45\% over the widely accepted standard IEEE 802.15.4 MAC protocol.

Wideband CMOS Amplifier Design: Time-Domain Considerations

Time-domain responses of wideband CMOS amplifiers using several inductive peaking techniques are presented. Transient performance considerations are described, including the effects of transistor parasitics on settling and edge rates. A combination of time-and frequency-domain performance is derived for a given bandwidth extension technique, and tradeoffs are discussed. Measured results for several high-speed high-gain single-stage amplifiers are presented in 0.18-mum CMOS, and a design strategy for multistage amplifiers is introduced. Finally, design and simulation results are presented for a multistage amplifier in 0.18-mum CMOS that attains a bandwidth of 22.7 GHz with 14.7-dB voltage gain, operates at 40 Gb/s, and consumes 93.6 mW.

A g/sub m/-Boosted Current-Reuse LNA in 0.18/spl mu/m CMOS

Demand for fully-integrated RF circuits offering low power consumption continues to grow, along with a strong desire for high performance. In this paper a design that enhances the performance of the common-gate LNA is detailed. The noise performance is improved through the use of a gm-boosting technique, while the gain performance is improved using current-reuse techniques. The proposed solution alleviates the issues related to the common-source-common-source current-reuse topologies. The technique is validated with a design in 0.18 mum CMOS, with a 5.4 GHz LNA which achieves >20 dB of gain, <3 dB NF and consumes only 2.7 mW of power.

Pulse-Width Modulated CMOS Power Amplifiers

The relentless scaling of CMOS circuits has led to the possibility of completely integrated RF-SOCs, including the PA. A CMOS PA likely will not achieve the same peak output power and efficiency as its counterpart in a III-V technology. It is conceivable, however, that by taking advantage of the strengths of CMOS switching devices, future CMOS PAs can win in terms of average efficiency and, perhaps more importantly, cost. PWM techniques offer one such potential solution, owing to the level of digital integration possible. Because of this, PWM PAs are expected to scale well, and the dynamic range possible with such amplifiers should increase as well because the faster devices will be able to process signals with smaller pulse widths.

A Quadrature Switched Capacitor Power Amplifier

This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65 nm CMOS. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array. The I/Q signals are digitally weighted and combined in the charge domain. Quadrature summation results in a 3 dB signal loss; Hence the Q-SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. Unlike polar/EER counterparts, the Q-SCPA requires no wideband phase modulator or delay matching circuitry. The Q-SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%. It is measured with a 10 MHz, 64 QAM LTE signal, and achieves an ACLR of <;-30 dBc, with an EVM <; 4%-rms.