David J. Allstot

Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis

This paper describes new techniques for the simulation and power distribution synthesis of mixed analog/digital integrated circuits considering the parasitic coupling of noise through the common substrate. By spatially discretizing a simplified form of Maxwells equations, a three-dimensional linear mesh model of the substrate is developed. For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel. For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. Macromodel simulations are significantly faster than device level simulations and compare accurately to measured results. Synthesis results demonstrate the critical need to constrain substrate noise and simultaneously optimize power bus geometry and pad assignment to meet performance targets. >

CMOS continuous-time current-mode filters for high-frequency applications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 mu m n-well CMOS process achieved a -3 dB cutoff frequency (f/sub 0/) of 42 MHz; f/sub 0/ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 mu A. Using a single 5 V power supply with a nominal reference current of 100 mu A, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm/sup 2//pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 mu m n-well CMOS process to verify the implementation of finite transmission zeros. >

Considerations for fast settling operational amplifiers

The design considerations for fast-settling operational amplifiers (op amps) are significantly different between sampled-data switched-capacitor (SC) and conventional continuous-time applications. In SC circuits, the shape of the output voltage waveform of an op amp is of no consequence provided that the output settles to within a specified tolerance of its steady-state value prior to the next sampling instant. This feature allows for an optimum op amp frequency shaping to obtain a minimum small-signal settling time. The theory applies to any op amp that is well approximated by a two-pole model, including the conventional two-stage and single-stage folded-cascode topologies. As the commonly used equivalent-circuit Miller-effect model for frequency compensation has generally been improperly applied to two-stage transconductance amplifiers, it does not provide sufficient accuracy to achieve the optimum phase margin condition. Therefore, the use of equivalent-circuit models has been refined to provide greater accuracy and to eliminate some previous misconceptions. >

Verification techniques for substrate coupling and their application to mixed-signal IC design

This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems.

Electrothermal simulation of integrated circuits

This paper describes new techniques for simulating the DC and steady-state thermal characteristics of integrated circuits using the incomplete Choleski conjugate gradient (ICCG) method, and transient electrothermal performance using an efficient macromodeling method based on asymptotic waveform evaluation (AWE). Results on several benchmark circuits show orders of magnitude reductions in CPU time and memory with accuracy comparable to that of the traditional techniques. >

Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs

CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing ( Delta V/sub L/ approximately=0.2 V/sub dd/) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2- mu m CMOS process, and simulated results with a standard 1- mu m process are used to compare the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies. >

Modeling of frequency and temperature effects in GaAs MESFETs

The small-signal conductance and large-signal I-V characteristics of conventional 1- mu m recessed-gate GaAs depletion-mode MESFET devices have been investigated. The small-signal saturation-region output conductance g/sub ds/ of a conventional GaAs MESFET is dependent on both frequency and temperature. These dependencies present serious difficulties in the design of many GaAs integrated circuits, since the small-signal voltage gain in analog circuits and the propagation delay in digital circuits depend on g/sub ds/, and no accurate simulation model is available. A semiempirical model for the frequency-dependent parameters in GaAs depletion-mode MESFETs is presented. An analytical formulation of temperature dependence is also included by an extension of the basic Curtice model. The resulting model is significantly more accurate than other models, which have not previously incorporated frequency- and temperature-dependent effects. >

CMOS folding A/D converters with current-mode interpolation

A CMOS folding and interpolating A/D conversion architecture fully compatible with standard digital CMOS technology is described. Fully-differential, continuous-time, current-mode, open-loop analog circuitry is used to achieve high speed. Results from 125 Ms/s 8-b and 150 Ms/s 6-b prototypes implemented in a digital 1 /spl mu/m n-well CMOS process are presented. The 8-b (6-b) converter occupies 4 mm/sup 2/ (2 mm/sup 2/) and dissipates 225 mW (55 mW) from a single 5 V power supply.

A continuous-time current-mode integrator

The authors propose a continuous-time current-mode integrator that offers potential advantages for both higher frequency and lower power monolithic filtering applications. Owing to the small voltage swings inherent in current-mode circuits, the integrator time constant is determined by a small-signal transconductance and an additional MOSFET gate capacitance, while good linearity is maintained using a standard 2- mu m digital CMOS technology. Simulation results predict passband cutoff frequencies exceeding 30 MHz for a five-pole low-pass filter dissipating as little as 2 mW/pole with a 5-V power supply. >

A methodology for rapid estimation of substrate-coupled switching noise

In this paper we present a methodology for rapid estimation of substrate coupled switching noise in mixed-signal chips. This methodology differs from existing approaches in that it does not require full chip, SPICE level transient or frequency domain simulations or long user-specified test vectors at the chip I/O. Instead, it relies on power dissipation data available from system-level power estimators and determines an estimate of the substrate coupled switching noise profile on the chip-substrate. This method trades off the accuracy available in existing approaches for improved execution times and significantly simpler user-inputs. Thus, this methodology is useful when rough estimates of substrate coupled switching-noise are adequate, for example, during manual or automatic system-level mixed-signal floorplanning.