Jeffrey W. Scott

z-domain model for discrete-time PLL's

The well-known s-domain model for continuous-time phase-locked loops (PLLs) is a fundamental tool for the linearized analysis of these systems. For PLLs with digital inputs and outputs, however, a discrete-time z-domain model more accurately describes loop behavior. In this study, a methodology is described for obtaining an accurate z-domain description of a discrete-time PLL. The modeling technique transforms portions of the s-domain PLL model directly into the z-domain, requiring only straightforward algebraic manipulations even for complex loop filters. This methodology is demonstrated for a simple loop filter, and measurements from the digital signaling interface integrated circuit are used to compare s-domain, z-domain, and time-step analysis results for a more complicated loop filter. The z-domain model, although only incrementally more complicated than the s-domain model, is shown to be more accurate, especially at higher jitter frequencies. >

A CMOS direct access arrangement using digital capacitive isolation

A Direct Access Arrangement (DAA) provides a customer interface to the public switched telephone network (PSTN). In addition to DC and AC termination and ring detect functions, the DAA must also provide high voltage isolation (>1500 V) between the phone network and system side devices while passing control information and a high integrity audio signal. This solution uses a capacitive isolation technique with a pair of 5 V 0.5 mm triple-metal CMOS devices in 16-pin SOIC packages that provides a digital communication link between the telephone line circuitry (isolated side) and the system side of the barrier. A few low-cost, high-voltage discrete components are added to interface the isolated-side device to the high-voltage telephone network.

A CMOS slope adaptive delta modulator

A slope adaptive A/D converter that reduces quantization noise through oversampling and feedback will be presented. A dynamic range of 90dB in the audio band, 15b resolution and total harmonic distortion of 0.17% at 1kHz has been achieved using a 3.5μm process.

A 16 Mb/s data detector and timing recovery circuit for token ring LAN

A 1.75- mu m CMOS interface circuit for a differential Manchester-coded 16-Mb/s token-ring local area network (LAN) is presented. The chip provides fixed gain and slicing functions as well as integrated clock recovery, data timing, and lock detection. When it is used in tandem with a digital controller/driver chip, a complete 16-Mb IEEE 802.5-1988 standard-compatible token-ring transceiver is realized. Block-level functionality of the interface circuit is discussed, following by more detailed subcircuit descriptions and a presentation of measured results. The measured jitter transfer function of the PLL phase-locked to a high-transition-density data stream is shown.<<ETX>>