Navdeep Singh Sooch

A monolithic 20 b delta-sigma A/D converter

Oversampled delta-sigma converters have been used for high-resolution analog-to-digital conversion over a wide range of input frequencies. Oversampled converters reduce the need for complex antialias filters, eliminate sample-and-hold amplifiers, and are free of differential nonlinearity errors. A fourth-order converter with a dynamic range of 123 dB and a signal-to-total-harmonic-distortion ratio of 126 dB is described. The input voltage range is 20 V peak to peak, the input signal bandwidth is DC to 500 Hz, the clock frequency is 1024 MHz, and the output word rate is 32 K/s. The 4.48*6.53-mm chip is packaged in a 28-pin plastic leaded chip carrier/leadless chip carrier (PLCC/LCC) and dissipates 120 mW using +5 V, -5 V, and ground.<<ETX>>

A CMOS direct access arrangement using digital capacitive isolation

A Direct Access Arrangement (DAA) provides a customer interface to the public switched telephone network (PSTN). In addition to DC and AC termination and ring detect functions, the DAA must also provide high voltage isolation (>1500 V) between the phone network and system side devices while passing control information and a high integrity audio signal. This solution uses a capacitive isolation technique with a pair of 5 V 0.5 mm triple-metal CMOS devices in 16-pin SOIC packages that provides a digital communication link between the telephone line circuitry (isolated side) and the system side of the barrier. A few low-cost, high-voltage discrete components are added to interface the isolated-side device to the high-voltage telephone network.

A monolithic line interface circuit for T1 terminals

The paper will cover an interface circuit capable of driving 25 ohm lines, that contains a pulse-shaping driver and a PLL for clock and data recovery. The circuit has been fabricated in 3μm CMOS.

Monolithic 20‐bit delta‐sigma A/D converter suitable for use in portable seismic data capture instrumentation

A monolithic CMOS ZO-bit analog-to-digital converter employing over-sampling techniques has been developed. The device contains a fourth order delta-sigma modulator and a digital finite-impulse-response filter and decimator. The analog input is sampled at a 256kHz rate and the digital words are output at a rate of 32kHz. The measured signal-to-noise and signal-to-total-harmonic-distortion ratios are 12OdB and LlOdB respectively. These specifications and a low power consumption of YOVLW make the device suitable for use in portable seismic data capture instrumentation.