Jen Hao Cheng

60-GHz 5-bit Phase Shifter With Integrated VGA Phase-Error Compensation

A 57-64-GHz low phase-error 5-bit switch-type phase shifter integrated with a low phase-variation variable gain amplifier (VGA) is implemented through TSMC 90-nm CMOS low-power technology. Using the phase compensation technique, the proposed VGA can provide appropriate gain tuning with almost constant phase characteristics, thus greatly reducing the phase-tuning complexity in a phased-array system. The measured root mean square (rms) phase error of the 5-bit phase shifter is 2° at 62 GHz. The phase shifter has a low group-delay deviation (phase distortion) of +/- 8.5 ps and an excellent insertion loss flatness of ±0.8 dB for a specific phase-shifting state, across 57-64 GHz. For all 32 states, the insertion loss is 14.6 ± 3 dB, including pad loss at 60 GHz. For the integrated phase shifter and VGA, the VGA can provide 6.2-dB gain tuning range, which is wide enough to cover the loss variation of the phase shifter, with only 1.86° phase variation. The measured rms phase error of the 5-bit phase shifter and VGA is 3.8° at 63 GHz. The insertion loss of all 32 states is 5.4 dB, including pad loss at 60 GHz, and the loss flatness is ±0.8 dB over 57-64 GHz. To the best of our knowledge, the 5-bit phase shifter presents the best rms phase error at center frequency among the V-band switch-type phase shifter.

Design of a 90.9% Locking Range Injection-Locked Frequency Divider with Device Ratio Optimization in 90-nm CMOS

A 12–32 GHz divide-by-2 (D2) injection-locked frequency divider (ILFD) is presented in this paper. First, the device ratio of the injection mixer and cross-coupled pair is optimized to achieve a wide locking range (LR). Then, the inductive peaking and forward-body-bias techniques are applied to the injection mixer to boost its transconductance and to enhance injection efficiency for further extension of the LR. Finally, the harmonic suppression technique is introduced to reduce the output harmonics. Using the aforementioned approaches, we successfully demonstrate a D2 ILFD implemented in the 90-nm low-power CMOS technology with a maximum LR of 90.9% at an injection power of 0 dBm. Even with the injection power as low as −10 dBm, the proposed ILFD maintains an LR of 32.9%. This ILFD consumes 2.4 mW with a supply voltage of 0.6 V in a chip size of 0.45 mm2.

A X-band digitally controlled 5-bit phase shifter in 0.18-μm CMOS technology

A X-band 5-bit switch type phase shifter (STPS) in 0.18-μm CMOS technology is presented in this paper. The proposed switched delay networks are using transmission lines to avoid process variation of small-size capacitors. For all 32 states, the insertion loss is -14 ± 3dB, including pad loss and the input and output return loss is > 8 dB over 8-12 GHz. The measzured rms amplitude error and rms phase error are smaller than 1.3 dB and 8.8°, respectively. The total chip size is 0.81 mm2, including pads with 0-mW dc power consumption.

A 24-GHz transformer-based stacked-FET power amplifier in 90-nm CMOS technology

A 24-GHz transformer-based stacked-FET power amplifier (PA) was designed in 90-nm CMOS technology. The stack configuration overcomes the low breakdown voltages of scaled transistors. The proposed power amplifier achieves a saturated output power of 21.7 dBm and 1-dB compressed output power (OP1dB) of 18.9 dBm with peak power-added efficiency (PAE) of 16.7% at 3-V supply voltage. The chip occupies an area of 0.53 × 0.51 mm2, including all the dc and RF pads.

A 0.33 V 683

An ultra-low-power transformer-based K-band receiver front-end is implemented in a 65 nm CMOS technology. For noise and input matching, a gate-to-source transformer-feedback technique is applied to the first-stage of the LNA. A transformer-based gain-boosting feedback technique is adopted in the second-stage of the LNA for further gain enhancement without additional dc power. Several transformers are utilized for inter-stage matching of the LNA and for single-to-differential LO/RF baluns of the ring mixer. By using forward-body-bias technique, the LNA operates at 0.33 V supply. For low-power receiver, a resistive ring mixer is adopted. The receiver demonstrates a 12.5 dB conversion gain (CG) and a 5.7 dB double-side band NF at IF frequency of 100 MHz with LO power of -10 dBm while consuming only 683 μW. To the best of our knowledge, the receiver demonstrates the lowest dc power consumption among recently reported K-band CMOS receiver.

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In this paper, a gm-boosted low-noise amplifier (LNA) with a low-voltage architecture is proposed to enhance gain and noise performance under low-power operation. It is designed at 5-GHz using 0.18-μm CMOS process. By employing current-reused, and forward-body-bias techniques, LNA can operate at a reduced supply voltage with micro-watt dc power consumption. In addition, gm-boosted topology using transformer-coupling is added to the LNA to further improve gain and to reduce noise factor simultaneously. Based on aforementioned techniques, the 5-GHz LNA presents a gain of 10.0 dB and a noise figure of 4.8 dB at 4.8 GHz. Under a supply voltage of 0.6 V, the dc power consumption is 336 μW.

K-Band Transformer-Based Receiver Front-End in 65 nm CMOS Technology

In this paper, a 6-GHz frequency synthesize (FS) for SATA III application by using 0.18-μm CMOS technology is presented. Multi-modulus divider (MMD) is utilized to achieve the function of spreading spectrum of SATA III. The complementary voltage-controlled oscillator (VCO) is adopted for phase noise consideration. In order to reduce the locking time of spreading spectrum, the loop bandwidth is increased as large as possible. Based on the aforementioned techniques, the measured free-running phase noise and closed-loop phase noise of the proposed FS are -112 dBc/Hz and -80 dBc/Hz at 1-MHz offset frequency, respectively. The total dc power consumption is 25.2 mW.

A 0.6-V 336-μW 5-GHz LNA using a low-voltage and gain-enhancement architecture

A 8GHz PLL for FMCW radar using 180-nm CMOS is presented in this paper. Utilizing a fractional-N synthesizer as the FMCW generator, it modulates the frequency across a range of 90 MHz. The phase noise of the proposed PLL is measured of -86.53 dBc/Hz at 1 MHz offset and -123 dBc/Hz at 10 MHz offset. The reference spur is -60 dBc. The dc power consumption is 32 mW under a 1.8-V supply.

A 6-GHz integer frequency synthesizer for SATA III applications in 0.18-μm CMOS technology

In this paper, a receiver front-end which contains variable gain amplifier (VGA) and Gilbert-cell-based I/Q mixer for 60-GHz heterodyne system in 65-nm CMOS technology is presented. The chip size is 0.91 × 1.515 mm2, including all the testing pads and dummy metals. The operation frequency of the proposed receiver front-end is from 4.32 GHz to 8.64 GHz. At a 1.0-V supply voltage, this front-end demonstrates the gain-control capability at linear region from 2.5 dB to 12.5 dB by adjusting the control voltage of the attenuator in VGA. The measured Psat is -11.7 dBm and it occurs at 2.5-dBm LO drive power where as RF frequency is at 7.48 GHz. The measured LO-to-IF and RF-to-IF isolation are better than 30 dB and 25 dB, respectively.

A X-band frequency synthesizer for FMCW radar in 180-nm CMOS

In this paper, a low-power K-band phase-locked loop (PLL) for vital sign detection radar (VSDR) is presented. The proposed PLL was fabricated in 0.18 μm CMOS process. The transformer-feedback voltage-controlled oscillator (TF-VCO) is utilized to increase output swing and to alleviate noise issue. The cascoded frequency divider is adopted for low voltage and low power considerations. The measured phase-locked-loop phase noise at 20.2 GHz is -110 dBc/Hz at 10 MHz offset frequency and the corresponding reference spur is -58 dBc. The locking range covers a frequency band from 19.2-20.6 GHz. The PLL dissipated 38 mW (with buffers) at 1.8-V supply voltage and occupies the chip area of 0.46 mm2.