Hong Yuan Yang

60-GHz 5-bit Phase Shifter With Integrated VGA Phase-Error Compensation

A 57-64-GHz low phase-error 5-bit switch-type phase shifter integrated with a low phase-variation variable gain amplifier (VGA) is implemented through TSMC 90-nm CMOS low-power technology. Using the phase compensation technique, the proposed VGA can provide appropriate gain tuning with almost constant phase characteristics, thus greatly reducing the phase-tuning complexity in a phased-array system. The measured root mean square (rms) phase error of the 5-bit phase shifter is 2° at 62 GHz. The phase shifter has a low group-delay deviation (phase distortion) of +/- 8.5 ps and an excellent insertion loss flatness of ±0.8 dB for a specific phase-shifting state, across 57-64 GHz. For all 32 states, the insertion loss is 14.6 ± 3 dB, including pad loss at 60 GHz. For the integrated phase shifter and VGA, the VGA can provide 6.2-dB gain tuning range, which is wide enough to cover the loss variation of the phase shifter, with only 1.86° phase variation. The measured rms phase error of the 5-bit phase shifter and VGA is 3.8° at 63 GHz. The insertion loss of all 32 states is 5.4 dB, including pad loss at 60 GHz, and the loss flatness is ±0.8 dB over 57-64 GHz. To the best of our knowledge, the 5-bit phase shifter presents the best rms phase error at center frequency among the V-band switch-type phase shifter.

A 30–100 GHz Wideband Sub-Harmonic Active Mixer in 90 nm CMOS Technology

This letter presents a 30-100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits -1.5 plusmn 1.5 dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm2. The OP1 dB of the mixer is -10.4 dBm and -9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.

1024-QAM High Image Rejection

An E-band high image-rejection sub-harmonic in-phase/quadrature (IQ) modulator for a high-order quadrature amplitude modulation (QAM) signal is designed and implemented on standard 65-nm CMOS technology. To maintain high image-rejection ratio of the IQ modulator over a wide bandwidth for high data-rate application, a load-insensitive analysis and a local oscillator (LO) broadband 45° power splitter are proposed to achieve low amplitude and phase imbalanced structure. In addition, the doubly balanced sub-harmonic Gilbert-cell mixer with the advantages of good LO leakage suppression has been selected in the mixer design. The IQ modulator demonstrates a measured flat conversion gain of 0 ± 1 dB from 55 to 85 GHz. The image rejection ratio is better than 40 dBc from 64 to 84 GHz. For millimeter-wave communication applications, the IQ modulator is integrated with a four-stage power amplifier to form a direct-conversion transmitter. The measured conversion gain of the transmitter is 33 dB and the measured saturated power is 11 dBm. Via high image rejection and good LO suppression of the modulator, a 1024-QAM modulated signal with a data rate of 500 Mb/s and 1.7% error vector magnitude is successfully demonstrated at 65 GHz.

E

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a Psat of 10.72 dBm and OP1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

-Band Sub-Harmonic IQ Modulator and Transmitter in 65-nm CMOS Process

Two V-band low-noise amplifiers (LNAs) with excellent linearity and noise figure (NF) using 90-nm CMOS technology are demonstrated in this paper, employing parasitic-insensitive linearization topologies, i.e., cascode and common source, for comparative purposes. To improve the linearity without deteriorating the NF, the 54-69-GHz cascode LNA is linearized by the body-biased post-distortion, and the 58-65-GHz common-source LNA is linearized by the distributed derivative superposition. Using these parasitic-insensitive linearization methods at millimeter-wave frequency, the cascode LNA can achieve an IIP3 of 11 dBm and an NF of 3.78 dB at 68.5 GHz with a gain of 13.2 dB and 14.4-mW dc power. The common-source LNA has an IIP3 of 0 dBm and an NF of 4.1 dB at 64.5 GHz with a gain of 11.3 dB and 10.8-mW dc power. To the best of our knowledge, the proposed cascode LNA has up to 11-dBm IIP3 performance and the highest figure-of-merit of 156.2, among all reported V-band LNAs.

A 60 GHz CMOS Power Amplifier With Built-in Pre-Distortion Linearizer

A new doubly balanced drain-pumped topology for CMOS passive mixer design is proposed in this paper. In the efforts to improve the conversion loss of passive balanced mixers, the CMOS drain-pumped topology is employed. In addition, the doubly balanced architecture with the advantages of good port-to- port isolations has been combined with the CMOS drain mixer de- sign. For the broad bandwidth and the flatness of the conversion loss, a wideband matching technique using a broadband Marchand balun network is analyzed and successfully implemented in the mixer design. This mixer is fabricated in standard 90-nm CMOS technology. According to experiment results, the mixer has a measured conversion loss of 7.5 ± 1.5 dB from 33 to 58 GHz. Based on the double-balanced architecture, the local oscillator (LO)-to-RF and LO-to-IF isolations are better than 42.7 and 51.5 dB, respectively. The mixer consumes zero dc power with a compact size of 0.55 × 0.52 mm2. To the best of our knowledge, this paper presents the first CMOS drain mixer using doubly balanced topology.

Parasitic-Insensitive Linearization Methods for 60-GHz 90-nm CMOS LNAs

This paper presents a miniature 38-48 GHz sub-harmonic transmitter with post-distortion linearization using a 0.15-mum GaAs HEMT process. The transmitter, which integrates a sub-harmonic mixer, a band-pass driver amplifier, and a linearizer, has a compact chip size of 2.5 mm2 with conversion gain of 7 plusmn 1.5 dB from 38 to 48 GHz. With the features of the sub-harmonic mixer and band-pass driver amplifier, the 2fLO leakage rejection of the transmitter is 47 dB. For the linearity of the transmitter, a post-distortion linearizer is added. After linearization, the output spectrum re-growth can be suppressed by 8 dB at 40 GHz. To keep ACPR below -35 dBc, the output power has been increased from -2 to 1 dBm, which means the linear output power has been doubled after linearization.