Jeng Gong

1/f noise in the linear region of LDD MOSFETs

A lightly doped drain (LDD) MOSFET can be decomposed as an intrinsic MOSFET in series with n/sup -/ source and drain regions. Under the assumption that the 1/f noise mainly comes from the intrinsic MOSFET part of the device, an expression for the drain noise power spectrum was developed in terms of terminal voltages. Noise measurements were performed on n-channel devices with effective channel lengths varying from 0.87 to 11.37 mu m. Good agreement between experimental values and theoretical values for a device channel length shorter than 4 mu m was obtained. It was also found that the LDD device has less noise than a conventional-structured MOSFET with the same channel length and operated under same terminal voltages. >

Mobile Charge Induced Breakdown Instability in 700V LDMOSFET

One chip solution for SMPS (switch mode power supply) has been drawing great attention of the designers with its green mode standby power and high efficiency in the AC-DC adaptor and LED lighting applications. The UHV (ultra-high voltage) foundry process, which enables the integration solution for green compliance SMPS, is proposed in this paper. The technology integrated low voltage CMOS (5 V), medium voltage (40 V) and UHV (700 V) devices in one single process. The UHV technology provides a novel UHV device structure with RESURF (Reduce-SURface-Field) effect to sustain ultra-high breakdown voltage and not to affect the original low/medium voltage devices performance in the same time. Thus, the concept of this novel structure is easily to apply to the other technology nodes and extend its voltage-sustaining range by adjusting the drift length for the RESURF structure. In this research, the 700 V technology has realized the performance that the BVdss (breakdown voltage) is 800 V with Ronsp (on-resistance) of 270 mOhm-cm2. In the same time, the process challenge to optimize 700 V device performance against un-balanced mobile charge issue was also discussed.

Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure

In this paper, early-stage hot-electron generation is shown to inject electrons into the shallow trench isolation (STI) edge above the drift region that causes the linear-region drain current to increase abruptly in the first moment of the stress for P-LDMOS transistors. After this early-stage carrier trapping, the transistor exhibits normal hot-carrier degradation during the following stress period. To further study this phenomenon, the geometry and the doping profile of the drift region near the STI edge and the polysilicon gate doping area are changed to investigate the initial IDLIN increase. Two-dimensional device simulator is used to analyze the experimental results. It is proven that the amount of current increase strongly depends on the distance from the maximum impact ionization generation rate point to the STI.

Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress

In this paper, a new reverse transconductance method for investigating the effect of hot-carrier degradation on high-voltage (HV) lateral diffused metal–oxide–semiconductor field-effect transistors (LDMOSFETs) is presented. This new method can extract asymmetric drain and source series resistance separately with only one single device. By using this extraction method in HV LDMOSFETs before and after the application of hot-carrier stress, drain series resistance is extracted and found to increase while source series resistance remains the same. In addition, the threshold voltage and subthreshold slope suffer no degradation after the application of hot-carrier stress. Therefore, it is suggested that the current degradation in HV LDMOSFETs after the application of hot-carrier stress is not due to the damage under the channel but is due to the drift region under the spacer oxide. This is confirmed by the simulation results of a two-dimensional (2D) simulator. In addition, the differences in hot-carrier degradation between HV LDMOSFETs and low-voltage lightly doped drain (LV LDD) MOSFETs are also discussed in detail.

Hot Carrier Degradation in Deep Sub-Micron Nitride Spacer Lightly Doped Drain N-Channel Metal-Oxide-Semiconductor Transistors

Spacer bottom oxide in the nitride spacer lightly doped drain (LDD) device, which is used to prevent huge interfacial states between the nitride and silicon interface, plays an important role in the hot carrier test. Because of the stress due to atomic size mismatch between the nitride spacer and silicon, trap-assisted hot electron tunneling is more significant in a nitride spacer LDD device than in the oxide spacer counterpart. A thicker bottom oxide can eliminate this effect. However, the optimal thickness of the nitride spacer bottom oxide should be varied for different poly-silicon gate structures. The hot carrier stress in a nitride spacer LDD device causes multi-stage degradation under Isub,max stress. It is dominated by electron trapping at the early stage, interfacial state (Nit) creation at the second stage, and self-limiting hot carrier degradation at the final stage. The degradation for Ig,max stress in nitride spacer LDD devices is mostly caused by electrons trapped in the nitride/oxide interface.

An analytical method of analyzing insulated-gate bipolar transistor characteristics in terms of applied terminal voltages

An analytical method of analyzing insulated-gate bipolar transistor (IGBT) current–voltage characteristics is established in this paper. Important internal device parameters such as the injected carrier concentrations, electron and hole current densities and depletion length of the drift region are calculated as functions of the terminal voltages. The parasitic transistor current gains αnpn and αpnp are also extracted as functions of applied voltages. The temperature effect on both latch-up criteria can also be predicted from this method.

The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress

Threshold voltage V/sub t/ extracted by g/sub m/-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance g/sub m/ and the corresponding gate-to-source voltage V/sub gs/ at which peak g/sub m/ occurs. It ultimately decreases the threshold voltage V/sub t/ extracted by the g/sub m/-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in g/sub m/-maximum extrapolation method.

The Study of the Electrothermal Property of High-Voltage Drain-Extended MOSFETs

In this paper, the relation between the surface electric field and the temperature distribution dependence on the drift-region doping concentration in a 30-V asymmetric drain-extended MOSFET is studied. For the case of high drift-region concentration, the drain resistance is low, and the current density is high, which induces a high nonuniform temperature distribution in the transistor, which in turn reduces the carrier mobility and causes a negative drain resistance. For the case of low drift-region concentration, a uniform temperature distribution is obtained. However, the different drift-region concentration changes the location of the maximum temperature from the gate-overlapped drift region for the high concentration case to the drain-side contact region for the low concentration case under the high VGS and VDS conditions. Therefore, the self-heating effect is also changed by the redistribution of the electric field in the drift region.

High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

An easy to implement high voltage NPN transistor is integrated in a low voltage (LV) thin (4.5 /spl mu/m) epi-layer BiCMOS process. In this high voltage (HV) bipolar transistor, the conventional N/sup +/-buried layer of the collector is replaced with a P/sup +/-buried layer. The breakdown voltage is higher than 90 V. High current gain (>140), high Early voltage (>500 V), and high frequency response (>1.3 GHz) are also obtained.

The base current degradation of poly-emitter BJTs under AC stress

A simple model for the analysis of the ac stress effect in poly-emitter bipolar transistors is presented. Apart from the reverse-bias induced hot-carrier effects, the forward-bias recovery effect is a key factor under ac stress, it obviously suppresses the base current degradation of the device which is caused during the reverse-bias periods. In this work, we derived the relationship between the excess base current and the stress time for different ac stress conditions. This model is verified with experimental results. >