Jeng-Jie Peng

ESD test methods on integrated circuits: an overview

ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by certain organizations, such as ESDA, AEC, EIA/JEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. There are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) pin-to-VSS, (2) pin-to-VDD, (3) pin-to-pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an overview among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses.

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

A methodology to verify the ESD and latchup reliability of CMOS cell libraries has been proposed. The ESD- or latchup-sensitive layout in the cell library can be found by this proposed methodology with DRC (design rules check) and ERC (electrical rules check), before the chip is fabricated. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the internal cores, the ESD and latchup reliability of CMOS ICs assembled by the verified cell library can be significantly improved without trial-and-error design modification and wafer fabrication.

Active device under bond pad to save I/O layout for high-pin-count SOC

To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 /spl mu/m one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).

ESD protection design and verification in a 0.35-/spl mu/m CMOS ASIC library

In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-/spl mu/m silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-/spl mu/m CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-/spl mu/m CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 /spl mu/m 1P4M 3.3 V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC ICs.

Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness

A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 /spl mu/m/0.5 /spl mu/m has been successfully improved from the original 450 V to become 675 V in a 0.25 /spl mu/m CMOS process.

Layout design on bond pads to improve the firmness of bond wire in packaged IC products

During the manufacture of IC products, the breaking of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the ICs. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6 /spl mu/m IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.