Chyh-Yih Chang

High-Current Characterization of Polysilicon Diode for Electrostatic Discharge Protection in Sub-Quarter-Micron Complementary Metal Oxide Semiconductor Technology

Polysilicon diodes used in sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies are characterized by transmission line pulse (TLP) measurement to investigate device characteristics in a high-current regime. The second-breakdown current (It2) of the polysilicon diode shows good linear dependence on the device junction perimeter. When the polysilicon diodes are connected in a stacked configuration for reducing parasitic capacitance, the stacked polysilicon diodes show no degradation in electrostatic discharge (ESD) robustness compared with a single polysilicon diode. Such CMOS process-compatible polysilicon diodes have been successfully used as on-chip ESD protection devices for GHz radio-frequency (RF) circuits.

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process-compatible to general sub-quarter-micron CMOS processes.

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.

Design of negative charge pump circuit with polysilicon diodes in a 0.25 /spl mu/m CMOS process

A charge pump circuit realized with the substrate-isolated polysilicon diode in the 0.25 /spl mu/m CMOS process is proposed. With the polysilicon diode, the stable negative voltage generation can be realized in general sub-quarter-micron CMOS process without extra process modification or additional mask layer. The device characteristic of polysilicon diode and the voltage waveforms of the negative charge pump circuit have been successfully verified in a 0.25 /spl mu/m CMOS process with grounded p-type substrate.

Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology

A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad is constructed by connecting multilayer metals and inserting additional diffusion layers into the substrate below the metal layers. The metal layers except top metal layer are designed with special patterns, which have smaller area than that in the traditional bond pad. Both the additional diffusion layers and patterned metal layers are used to reduce the parasitic capacitance of bond pad. An experimental test chip has been designed and fabricated to investigate the reduction of parasitic capacitance of the bond pad. The bonding reliability tests on the fabricated bond pad, including the ball-shear and wire-pull tests, are also used to verify the bonding adhesion. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The new proposed bond pads can also keep the same good bonding reliability as that of a traditional bond pad.

Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is very useful for high-frequency ICs, which need a very low input capacitance.

On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

ESD protection in RF integrated circuits has several considerations: low parasitic capacitance, constant input capacitance, and insensitive to substrate coupling noise. In this paper, a new ESD protection design with polysilicon diodes for RF IC applications is proposed and characterized. The proposed polysilicon diode is constructed by a polysilicon layer in a general CMOS process with a central un-doped region. The polysilicon diode with variation on the width of the central un-doped region is characterized at different temperatures. An on-chip ESD protection circuit realized with the stacked polysilicon diodes to reduce the total input capacitance for GHz RF application is demonstrated.

Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process

Different electrostatic discharge (ESD) devices in a 0.35-/spl mu/m silicon germanium (SiGe) RF BiCMOS process are characterized in detail by a transmission line pulse (TLP) generator and ESD simulator for on-chip ESD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been fabricated to investigate their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), high-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.