Jeng-Shyan Lin

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.

Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

To address the integration of the high-mobility Ge/III-V MOSFET, a common gate stack (CGS) solution is proposed for the first time and demonstrated on Ge and InGaAs channels with combined hole and electron field-effect mobility values up to 400cm2/eV-s and 1300cm2/eV-s. Based on the duality found on the InGaAs/Ge MOS system, this approach aims to integrate the InGaAs/Ge MOSFET processes for high performance CMOS applications with an emphasis on progressive EOT scaling.

Crosstalk improvement technology applicable to 0.14/spl mu/m CMOS image sensor

For pixel crosstalk improvement, modified logic technology with thin epi wafer thickness, thin backend process thickness and air gap guard ring technology, pixel size can be further scaled down to less than 2.8 /spl mu/m /spl times/ 2.8 /spl mu/m and maintain the same performance as 4.0 /spl mu/m /spl times/ 4.0 /spl mu/m pixel does. Greater than 65% crosstalk reduction at 10/spl deg/ incident angle has been demonstrated. This technology can be applicable to CMOS image sensor with 0.14 /spl mu/m design rules.

Air-gap guard ring for pixel sensitivity and crosstalk improvement in deep sub-micron CMOS image sensor

An air-gap guard ring around the pixel sensor, to improve pixel sensitivity and crosstalk, in 0.18 /spl mu/m CMOS image sensor technology has been successfully developed. By using the RI (refractive index) difference between the air gap (RI/spl sim/1) and dielectric films (RI=1.4/spl sim/1.6), the major incident light is collected in the targeted pixel due to the total internal reflection occurred in the air-gap/dielectric-film interface. The small pixel pitch of 2.8 /spl mu/m/spl sim/4.0 /spl mu/m has been characterized and demonstrates excellent optical performance. For a 3.0 /spl mu/m pixel, the pixel sensitivity shows 45% enhancement and optical spatial crosstalk achieves 90% reduction at 20/spl deg/ incident angle.

Active pixel image sensor scale down in 0.18 /spl mu/m CMOS technology

A high performance 0.18 /spl mu/m CMOS image sensor technology is reported in this paper. It is modified from a generic logic technology. A 64/spl times/64 3T pixel array of various pixel size from 2.8 /spl mu/m to 4.0 /spl mu/m is used to study the scale down issues. By optimizing the process flow, the image sensors with the pixel size downscaled to 2.8 /spl mu/m demonstrates the high sensitivity, low dark current, low white pixel rate and high dynamic range. Although the crosstalk effect is getting worse for smaller pixel size, the 3 /spl mu/m pixel array demonstrates an excellent color rendition capability.