Dun-Nian Yaung

High mobility β-SiC epilayer prepared by low-pressure rapid thermal chemical vapor deposition on a (100) silicon substrate

Abstract The mobility of β-SiC thin films grown on (100) Si substrates by low-pressure rapid thermal chemical vapor deposition (LP-RTCVD) has been found to have a 200% improvement over that prepared by conventional low-pressure CVD. The SiC growth is achieved using a C 3 H 8 -SiH 4 -H 2 reaction gas system at a reduced pressure of 2.5 Torr. Both X-ray and transmission electron microscopy patterns show that the grown layer is single-crystal β-SiC. The influence of the growth conditions on the electrical properties of the SiC layer was also investigated. It was found that the maximum electron mobility can reach 254 cm 2 V −1 s −1 for carrier concentrations of (1–4) × 10 17 cm −3 and at substrate temperature of 1 150 °C. The electron mobility is the highest one reported to date for the low-pressure heteroepitaxial SiC films on Si substrates.

Nonsilicide source/drain pixel for 0.25-/spl mu/m CMOS image sensor

A nonsilicide source/drain pixel is proposed for high performance 0.25-/spl mu/m CMOS image sensor. By using organic material spin coat and etch back, silicide is only formed on poly gate which can be used as interconnection, not for source/drain region that solve the optical opaqueness and undesirably large junction leakage of silicide. The performance of MOSFET changes little due to the high sheet resistance of nonsilicide source/drain. With H/sub 2/ annealing and double ion implanted source/drain junction, the dark current can be further reduced. The novel pixel (three transistors, 3.3 /spl mu/m/spl times/3.3 /spl mu/m, fill factor: 28%) shows low dark current (less than 0.5 fA per pixel at 25/spl deg/C) and high photoresponse.

A novel /spl beta/-SiC/Si heterojunction backward diode

In this letter, a novel /spl beta/-SiC/Si heterojunction backward diode has been developed successfully. The developed new backward diode is somewhat different from a conventional one. The /spl beta/-SiC thin film was grown by a low pressure rapid thermal chemical vapor deposition (LP-RTCVD) using a SiH/sub 4/-C/sub 3/H/sub 8/-H/sub 2/ gas system. Its current-voltage characteristics under different operation temperatures (25-200/spl deg/C) have been measured. In addition, the curvature coefficient /spl gamma/ has also been calculated and it is found to be insensitive to temperature variation up to 180/spl deg/C. The operation temperature is the highest reported thus far, to our knowledge.<<ETX>>

Narrow width effects of bottom-gate polysilicon thin film transistors

The effects of channel width on the characteristics of both hydrogenated and unhydrogenated bottom-gate polysilicon thin-film transistors (TFTs) were investigated in detailed. For unhydrogenated and silane gas formed TFTs, a drastic decrease in threshold voltage is observed due to the grain-boundary traps are reduced when the channel width is reduced to less than grain size, but the minimum drain current sensitive to intragranular tail states are nearly unchanged. After hydrogenation, almost grain boundary traps and intragranular tail states were passivated, the effect of traps along poly channel edges caused by the definition of poly channel pattern will dominate, i.e., threshold voltage and minimum drain current increase with decreasing channel width. Also disilane gas formed TFTs are studied for comparison.

To suppress photoexcited current of hydrogenated polysilicon TFTs with low temperature oxidation of polychannel

In this letter, a short time low temperature oxidation of poly-Si channel has been studied to suppress the photoexcited current of the hydrogenated poly-Si TFTs. The effect of the treatment, which contains different-time oxidation and different-time post-hydrogenation, on the dark-current and photocurrent of poly-Si TFTs under off state were investigated in detail. An optimal combination of both technologies has been proposed according to the investigation. The poly-Si TFTs treated with the optimal process can be operated well under a high illumination environment.

Mechanism of device instability for unhydrogenated polysilicon TFTs under off-state stress

The effects of off-state stress (Vgs = 0 V, Vds = 0 to -20 V) on unhydrogenated p-channel polysilicon thin-film transistors (TFTs) were studied. It was observed that the post-stressed subthreshold swing is first improved due to the annealing effect from the interaction of tunnelling electrons and captured holes. As the stress time increases or as the stress bias increases, the generation of traps caused by tunnelling electrons will cancel out the annealing effect and then degrade the subthreshold swing. In addition, the trapping of tunnelling electrons in the gate oxide causes a shift of threshold voltage. However, improving the quality of the gate oxide interface by oxidation of the channel polysilicon on submicrometre bottom-gate TFTs can reduce the impact of the off-state stress.

Visible electroluminescence from a novel β‐SiC/p‐Si n‐p heterojunction diode prepared by rapid thermal chemical vapor deposition

A novel structure of β‐SiC/p‐Si has been reported to emit visible electroluminescence (EL). The β‐SiC is grown directly on a Si substrate by rapid thermal chemical vapor deposition (RTCVD) technology. The mechanism of EL emission is shown as a porous silicon (PS) layer. The PS is formed unintentionally at β‐SiC/p‐Si interface owing to a large lattice mismatch (20%) between β‐SiC and Si substrates. In addition, the heterojunction diode exhibits excellent rectifying behavior. The ideality factor n and rectification ratio at 1.0 V are 1.8 and 340, respectively.

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

In this paper, the mechanism of programming operation considering the source-to-floating gate coupling ratio (SCR) in split-gate source-side injected flash memory has been discussed and experimentally demonstrated. The effects of SCR on the programming performance and cycling endurance have also been investigated in detail. The experimental results indicate that the cell with higher SCR possesses a higher programming speed. Under the same programming speed, the higher-SCR cell shows larger cycling endurance compared to lower-SCR cell.

A novel programming technique for highly scalable and disturbance immune flash EEPROM

Abstract The program speed of a selected cell and the program disturbance of unselected cells sharing the common program-line in split-gate source-side injected flash memory has been investigated. It is found that the program disturbance becomes severe as the control gate length decreases. In this letter, we first propose a novel program technique by applying a negative bias to inhibited word-line to improve the trade-off between program speed and program disturbance. The experimental results indicate that the new program technique is a good candidate for future high-density, high-disturbance-immunity flash EEPROM memory applications.

High performance submicron bottom gate TFTs with self aligned Ti-silicide interpoly contact and poly-channel oxidation for high-density SRAM

Abstract A self-aligned Ti-silicide interpoly contact for submicron bottom-gate TFT-SRAM with poly-channel oxidation is presented. In this new scheme, oxidation of poly-channel improves subthreshold swing and leakage current of TFTs, but degrades cell stability because of voltage drop across interpoly contact. Using a-Si/Ti bilayer process on backside oxide of poly-channel after channel oxidation and interpoly contact definition, self-aligned Ti-silicide interpoly contact can be formed and voltage drop across the interpoly contact can be greatly reduced. As a result, low subthreshold swing and high on/off ratio for unhydrogenated TFT in series with interpoly contact has been realized.