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Jeng-Ya D. Yeh

Intel

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Publication

Featured researches published by Jeng-Ya D. Yeh.

Archive | 2011

Antifuse element utilizing non-planar topology

Walid M. Hafez; Chia-Hong Jan; Curtis Tsai; Joodong Park; Jeng-Ya D. Yeh

Archive | 2016

ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES

Walid M. Hafez; Chia-Hong Jan; Jeng-Ya D. Yeh; Hsu-Yu Chang; Neville Dias; Chanaka Munasinghe

Archive | 2014

Precision resistor for non-planar semiconductor device architecture

Jeng-Ya D. Yeh; Peter J. Vandervoorn; Walid M. Hafez; Chia-Hong Jan; Curtis Tsai; Joodong Park

Archive | 2015

HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS

Walid M. Hafez; Jeng-Ya D. Yeh; Curtis Tsai; Joodong Park; Chia-Hong Jan; Gopinath Bhimarasetti

Archive | 2013

Low leakage non-planar access transistor for embedded dynamic random access memeory (edram)

Joodong Park; Gopinath Bhimarasetti; Rahul Ramaswamy; Chia-Hong Jan; Walid M. Hafez; Jeng-Ya D. Yeh; Curtis Tsai

Archive | 2013

NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER

Jeng-Ya D. Yeh; Chia-Hong Jan; Walid M. Hafez; Joodong Park

Archive | 2013

CMOS-COMPATIBLE POLYCIDE FUSE STRUCTURE AND METHOD OF FABRICATING SAME

Jeng-Ya D. Yeh; Chia-Hong Jan; Walid M. Hafez; Joodong Park

Archive | 2013

Transistor architecture having extended recessed spacer and source/drain regions and method of making same

Walid M. Hafez; Joodong Park; Jeng-Ya D. Yeh; Chia-Hong Jan; Curtis Tsai

Archive | 2016

Vertical non-planar semiconductor device for system-on-chip (soc) applications

Chia-Hong Jan; Walid M. Hafez; Curtis Tsai; Jeng-Ya D. Yeh; Joodong Park

Archive | 2011

Multi-gate transistors

Chia-Hong Jan; Curtis Tsai; Joodong Park; Jeng-Ya D. Yeh; Walid M. Hafez

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Chia-Hong Jan

Intel

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Walid M. Hafez

Intel

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Joodong Park

Intel

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Curtis Tsai

Intel

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Gopinath Bhimarasetti

Intel

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Chanaka Munasinghe

Intel

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Neville Dias

Intel

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Hsu-Yu Chang

Intel

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Peter J. Vandervoorn

Intel

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Rahul Ramaswamy

Intel

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