Walid M. Hafez

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.

A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um2) and low voltage (0.171 um2) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.

A 1.1 GHz 12

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.

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The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cut-off frequency (fT) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.

A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured fT/fMAX values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm Lgate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm L_gate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve f_T/f_MAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with f_T/f_MAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology is also discussed

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2 low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moores Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an fT of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an fT of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High Q inductors, >7V breakdown voltage power amplifier transistors, varactors, and precision passives are also presented.

A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products

A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01μm2. The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability.