Jennifer L. H. Webb

Open multimedia application platform: enabling multimedia applications in third generation wireless terminals through a combined RISC/DSP architecture

Describes how multimedia applications will be enabled in 3G wireless terminals thanks to the efficiency of the DSP core embedded in the TI Open Multimedia Application Platform (OMAP). The OMAP H/W architecture is described, with an emphasis on how multimedia applications (video, audio, speech) will benefit from this advanced architecture. The paper also depicts the advantages provided by a combined RISC/DSP architecture, compared to a single RISC architecture, for 3G multimedia mobile applications.

A simple rate-distortion model, parameter estimation, and application to real-time rate control for DCT-based coders

This paper describes a simple rate-distortion model, shows how the model parameters can be estimated using Kalman filtering, and suggests how this information may be used for rate control in real-time systems. Real-time parameter estimation is more robust with the simplified model, and the model yields useful insights. Also, the suggested Kalman filter is computationally efficient, and adapts to changes in the video sequence. Several uses of the model and parameter estimates are suggested for real-time rate control.

Efficient table access for reversible variable-length decoding

A new method for reversible variable-length codes (RVLC) decoding is described, which decreases the amount of table space required, particularly for MPEG-4 video RVLC decoding on a DSP chip. Because of the special structure of RVLC codewords, the decoding techniques that are common for regular VLCs are less efficient when used with RVLCs. The new method does not use the codeword itself to access a lookup table, but instead forms a sort of hash index. This reordering can significantly decrease the amount of memory required by reducing gaps or redundancy in the table entries.

Postprocessing to reduce blocking artifacts for low bit-rate video coding using chrominance information

We investigate a new postprocessing approach to reduce blocking artifacts in DCT-based video compression. Because blocking artifacts occur due to quantization of DCT coefficients, we effectively adjust the low-order DCT coefficients to remove discontinuities at block corners in smooth areas of the image. For blocking in detailed areas of the image, we camouflage black corners by adding a noisy dither to pixels around the block border. We demonstrate that chrominance variance can be used to efficiently identify blocks containing luminance detail. This postprocessing method is effective in reducing severe blocking effects that can occur at low bit rates. Examples from postprocessed H.261 video are given.

MPEG-4 Video and Image Coding on Digital Signal Processors

The emerging MPEG-4 standard encompasses a wide variety of applications, many of which are suitable for implementation on a Digital Signal Processor (DSP). In particular, consumer products with embedded multimedia capability, such as set-top boxes and wireless communicators, are suitable for DSP-based implementation. With a programmable approach, various algorithmic tradeoffs can be made, based on processing capability. For best performance, careful attention must be paid to memory allocation, data transfer, and ordering of instructions to best match the DSP architecture. We discuss implementing simple profile MPEG-4 video on the low-power TMS320C54x, core profile on the TMS320C6x, and scalable texture profile, which could be implemented on either processor family.

Wireless MPEG-4 video on Texas Instruments DSP chips

Technology has advanced in recent years to the point where multimedia communicators are beginning to emerge. These communicators are low-power, portable devices that can transmit and receive multimedia data through the wireless network. Due to the high computational complexity involved and the low-power constraint in wireless applications, these devices require the use of processors that are powerful and are at the same time very power-efficient. In order to facilitate interoperability, it is important that these devices use standardized compression and communication algorithms. As a first step in implementing multimedia terminals, Texas Instruments (TI) has demonstrated real-time MPEG-4 video decoding (simple profile) on TMS320C54x, TIs low power, high performance DSP chip. In addition, TI has outlined a system-level solution to transmitting video across wireless networks, including channel coding and communication protocols.

Macroblock quantizer selection for H.263 video coding

We consider two MSE-based strategies for selecting the best quantization parameter (Q) for each coded macroblock in H.263 video coding. In the first study, Q was adjusted to match a target mean-squared error (MSE) for each block. The goal was to avoid having large errors in a few macroblocks that detract from the overall perceived image quality. Effectively, we minimized the peak MSE over all macroblocks. In the second study, we sought to minimize the average MSE, modifying a gradient-search technique that has been applied to H.261. The choice of quantizers was limited by the H.263 syntactical constraints on changes in Q between successively-coded macroblocks. The results were compared with fixed Q encoding. The resulting sequences displayed only small perceptual differences. For the cases studied, the primary advantage of varying Q was to control the delay.

HRD Conformance for Real-time H.264 Video Encoding

The H.264 hypothetical reference decoder (HRD) ensures interoperability and smooth playback of video. Because the encoded bit rate may not match the channel rate, buffering and timing information must be specified for the decoder. These parameters can be obtained by analyzing a prerecorded bitstream, but if the video is encoded and transmitted in real-time, these parameters effectively constrain the rate control. We discuss how to set these parameters for real-time encoding, without having the entire bitstream available, and also how VProve can be used to verify HRD conformance.

Transposed FIR filter structure with time-varying coefficients for digital data resampling

A new time-domain derivation is presented for interpolation and decimation by a fractional factor U/D. Though it is well known that such a filter can be implemented using a direct-form I, FIR filter with time-varying coefficients, a novel time-varying alternative, using a transposed filter structure, is described. Time-varying filters are especially important for implementation on a digital signal processor. The new time-varying structure has the advantage of reduced buffer memory for downscaling, or increased parallelism for high-speed upscaling, compared to the conventional time-varying structure.

Enabling multimedia applications in 2.5G and 3G wireless terminals through a combined RISC/DSP architecture: OMAP

This paper describes how multimedia applications will be enabled in 2.5 and 3G wireless terminals thanks to the efficiency of the DSP core embedded in the TI OMAP platform. OMAP H/W architecture will be described with an emphasis on how multimedia applications (video, audio, speech) will benefit from this advanced architecture. The advantages provided by a combined RISC/DSP architecture, compared to a single RISC architecture, for multimedia mobile applications will be depicted.ZusammenfassungDer vorliegende Beitrag zeigt, wie die neue OMAP-Plattform von Texas Instruments, die einen DSP-Kern aufweist, multimediale Anwendungen in 2.5G- und 3G-Mobiltelefonen unterstützt. Die Autoren beschreiben die OMAP-Hardwarearchitektur und zeigen, wie zum Beispiel Video-, Audio- und Sprachanwendungen von dieser neuartigen Architektur profitieren. Die Vorzüge einer kombinierten RISC/DSP-Architektur im Vergleich zu einer reinen RISC-Architektur werden eingehend diskutiert.