Jens Schönherr

Digital high-pass filter deconvolution by means of an infinite impulse response filter

Abstract In the application of semiconductor detectors, the charge-sensitive amplifier is widely used in front-end electronics. The output signal is shaped by a typical exponential decay. Depending on the feedback network, this type of front-end electronics suffers from the ballistic deficit problem, or an increased rate of pulse pile-ups. Moreover, spectroscopy applications require a correction of the pulse-height, while a shortened pulse-width is desirable for high-throughput applications. For both objectives, digital deconvolution of the exponential decay is convenient. With a general method and the signals of our custom charge-sensitive amplifier for cadmium zinc telluride detectors, we show how the transfer function of an amplifier is adapted to an infinite impulse response (IIR) filter. This paper investigates different design methods for an IIR filter in the discrete-time domain and verifies the obtained filter coefficients with respect to the equivalent continuous-time frequency response. Finally, the exponential decay is shaped to a step-like output signal that is exploited by a forward-looking pulse processing.

Compositional verification of material handling systems

The design of properly working material handling systems (MHS) is a difficult process as these systems consist of a vast number of single elements with dedicated controls. While currently these systems are usually validated using simulation, formal methods provide a means to analyze the complete behavior of a system. However, these methods can often only be applied to systems of a moderate size, which hampers their application to verify real-world systems. This paper presents an approach to the compositional verification of MHS, which is based on the theory of assume-guarantee reasoning. The approach has been implemented in a tool that automatically carries out the verification. The application of the approach is shown using a real-world example.

On the formal verification of routing in material handling systems

The correct design of complex material handling systems (MHS) is a challenging task, mainly because of short development cycles and ever increasing system sizes. For baggage handling systems (BHS) at airports, the correct design of routing strategies is of special importance, as these strategies are non-trivial but safety-critical. This paper presents a novel approach to prove the correctness of routing in MHS. The approach is based on assume-guarantee reasoning which allows to derive proofs of the overall system using a divide and conquer strategy. The proposed approach is automated and has been implemented in a tool. The application of the approach is shown using a real-world BHS.

Formal verification for microprocessors with extendable instruction set

The correctness of processors is a key for their application. Although some verification methods were developed and successfully applied to conventional microprocessors, only a few of them were used in the context of application specific devices. This work introduces a formal verification approach for a reconfigurable microprocessor with extendable instruction set. The application of this approach is demonstrated using register transfer description of the CoMPARE processor and the Stanford Validity Checker as prover. Some undesired side effects of different instructions that were not discovered during the simulation were found by the verification process. In addition some deficiencies of the hardware description notation as specification formalism were shown.

Hazard checking in pipelined processor designs using symbolic model checking

The high speed requirements on todays processors can be met by pipeline architectures, but pipeline structures cause hazards, which are their main drawback. In principle there are two ways to handle hazards: the compiler avoids hazard-causing code sequences or the hardware treats the hazard situations. We propose a method which allows the computation of all code sequences that cause control hazards. Our method can be divided into two steps. First we model the relevant behavior of the processor as a finite state machine (FSM). The modeling is carried out by an abstraction of the behavioral description of the processor which preserves the properties that are relevant for hazard checking. In the second step we determine the hazard-causing code sequences by applying symbolic model checking. In contrast to other model checking tools, which compute a single counter example only, our model checker allows the generation of all hazard-causing code sequences.

Automated Formal Verification of Routing in Material Handling Systems

The design of correctly implemented controls in material handling systems (MHS) is time consuming and cumbersome. The developer has to deal with an ever increasing complexity and heterogeneity of MHS on the one hand, but also with short development cycles and high demands to MHS on the other hand. For baggage handling systems (BHS) at airports, the error-free implementation of routing strategies is especially of importance, as these strategies are critical to safety. This paper proposes a compositional approach to the formal verification of routing in MHS. The approach is based on the theory of assume-guarantee reasoning, where proofs of the overall system are derived from proofs of subsystems. Moreover, the approach has been implemented in a tool that automatically carries out the verification. A real-world example is discussed in this paper, showing the benefits and scalability of the presented approach.

Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

In this article, a verification methodology for mixed-signal circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits.

Formal Verification of a Reconfigurable Microprocessor

The increasing acceptance of reconfigurable logic in form of FPGAs or CPLDs has caused new research activities in the field of processor architecture, the reconfigurable processors. The basic idea consists in combining the flexibility of reconfigurable logic with the transparent and well-known instruction set programming model. In this way critical parts of the application can be implemented directly in hardware. It has been shown that reconfigurable microprocessors are able either to achieve speed-ups or to improve the cost/performance ratio for a broad range of applications [1].

Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level

One of the big challenges in circuit design is the formal verification at clocked algorithmic or register-transfer level. To overcome the limits of BDD based approaches we apply an abstraction of the datapath by uninterpreted functions. Symbolic execution is used to generate potential invariants. Then the equivalence is proven by automatic induction proofs of the lemmas.