Sergej Sawitzki

Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays

Conventional approaches to increase the performance of microprocessors often do not provide the performance boost one has hoped for due to diminishing returns. We propose the extension of a conventional hardwired microprocessor with a reconfigurable logic array, integrating both conventional and reconfigurable logic on the same die. Simulations have shown that even a comparatively simple and compact extension allows performance gains of 2–4 times over conventional RISC processors of comparable complexity, making this approach especially interesting for embedded microprocessors.

Improving code efficiency for reconfigurable VLIW processors

High code efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance code efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the code generation phase, which complicates scheduling and may lead to code deficiencies if resource conflicts occure. This paper discusses code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object code.

A Concept for an Evaluation Framework for Reconfigurable Systems

The design of reconfigurable systems is a hard task due to a huge amount of optimization trade-offs and constraints. Deficiencies at the higher level of conceptual decisions may result in critical bottlenecks of the system implementation. This paper explores the design space and performance evaluation criteria of reconfigurable systems and introduces a concept for an evaluation framework based on these explorations helping to avoid such deficiencies.

Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic

This paper compares selected digital signal processing algorithms on a variety of computing platforms in terms of achievable performance and cost. The experiments were carried out on a standard PC platform, DSP, a RISC microcontroller and on Xilinx XC4013XL FPGA. Our results confirm that general purpose microprocessors are not well suited to these tasks. Both DSP and FPGA achieve higher performance and/or better cost/performance ratios at the expense of lesser generality and a more complicated development cycle. The porting of the algorithms to DSP and FPGA requires about the same amount of work, whereby the cost/performance ratio of the reconfigurable FPGA solution is very attractive.

Formal verification for microprocessors with extendable instruction set

The correctness of processors is a key for their application. Although some verification methods were developed and successfully applied to conventional microprocessors, only a few of them were used in the context of application specific devices. This work introduces a formal verification approach for a reconfigurable microprocessor with extendable instruction set. The application of this approach is demonstrated using register transfer description of the CoMPARE processor and the Stanford Validity Checker as prover. Some undesired side effects of different instructions that were not discovered during the simulation were found by the verification process. In addition some deficiencies of the hardware description notation as specification formalism were shown.

Formal Verification of a Reconfigurable Microprocessor

The increasing acceptance of reconfigurable logic in form of FPGAs or CPLDs has caused new research activities in the field of processor architecture, the reconfigurable processors. The basic idea consists in combining the flexibility of reconfigurable logic with the transparent and well-known instruction set programming model. In this way critical parts of the application can be implemented directly in hardware. It has been shown that reconfigurable microprocessors are able either to achieve speed-ups or to improve the cost/performance ratio for a broad range of applications [1].

Gestaltung und Simulation hardware-rekonfigurierbarer Rechnersysteme

Rechnersysteme mit rekonfigurierbarer Hardware haben insbesondere in letzter Zeit an Bedeutung gewonnen. Wahrend es viele leistungsfahige Einzellosungen gibt, fehlt es bisher an allgemeiner Entwurfssystematik und durchgangiger Werkzeugunterstutzung fur solche Systeme. Im Rahmen eines Forschungsvorhabens im Graduiertenkolleg 191 „Werkzeuge zum effektiven Einsatz paralleler und verteilter Rechnersysteme“ werden Ansatze und Methoden zur Losung dieses Problems erarbeitet. In diesem Beitrag werden nach einer Kurzvorstellung des Graduiertenkollegs die bisher erreichten Ergebnisse prasentiert.