Jens Spinner

A CONFIGURABLE BOSE–CHAUDHURI–HOCQUENGHEM CODEC ARCHITECTURE FOR FLASH CONTROLLER APPLICATIONS

Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of the ECC unit is taking up a significant share of the overall logic. Scaling the ECC strength to the growing error correction requirements has become increasingly difficult when considering cost and area limitations. This work presents a configurable encoding and decoding architecture for binary Bose–Chaudhuri–Hocquenghem (BCH) codes. The proposed concept supports a wide range of code rates and facilitates a trade-off between throughput and space complexity. Commonly, hardware implementations for BCH decoding perform many Galois field multiplications in parallel. We propose a new decoding technique that uses different parallelization degrees depending on the actual number of errors. This approach significantly reduces the number of required multipliers, where the average number of decoding cycles is even smaller than with a fully parallel implementation.

A Soft Input Decoding Algorithm for Generalized Concatenated Codes

This paper proposes a soft input decoding algorithm and a decoder architecture for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In this paper, a representation of the block codes based on the trellises of supercodes is proposed in order to reduce the memory requirements for the representation of the BCH codes. This enables an efficient hardware implementation. The results for the decoding performance of the overall GC code are presented. Furthermore, a hardware architecture of the GC decoder is proposed. The proposed decoder is well suited for applications that require very low residual error rates.

Generalized concatenated codes for correcting two-dimensional clusters of errors and independent errors

Correction of two-dimensional error clusters is required in many storage systems. Most known error correction systems for such errors are based on two-dimensional interleaving and interleaved codes. However, interleaved codes are not well suited to correct additional independent errors. This work proposes a novel combination of generalized concatenated codes with two-dimensional interleaving to correct two-dimensional error clusters and independent errors.

Concatenated code constructions for error correction in non-volatile memories

This work investigates and compares different coding techniques for error correction in multilevel NAND flash memories. In particular, we consider strong error correction codes with an overall code rate of 0.8 and with a sector size of 1 kbyte. Two concatenated code constructions are compared to the state-of-the-art Bose-Chaudhuri-Hocquenghem (BCH) codes. First, we consider a serial concatenation of an outer BCH code and an inner LDPC or turbo code (TC). The second construction is a generalized concatenated code with outer Reed-Solomon (RS) and inner BCH codes. The presented simulation results and theoretical investigations demonstrate that the algebraic code constructions obtain a performance close or even superior to the iterative coding schemes.

Construction of High-Rate Generalized Concatenated Codes for Applications in Non-Volatile Flash Memories

This work proposes a construction for high-rate generalized concatenated (GC) codes. The proposed codes are well suited for error correction in flash memories for high reliability data storage. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. For the inner codes we propose extended BCH codes, where we apply single parity-check codes in the first level of the GC code. This enables high-rate codes.

Design and Implementation of a Pipelined Decoder for Generalized Concatenated Codes Format

This article proposes a pipelined decoder architecture for generalized concatenated codes (GCC). These codes are constructed from inner binary Bose-Chaudhuri-Hocquenghem (BCH) and outer Reed-Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GCC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GCC decoder achieves a higher throughput and has lower area consumption.

Mixed serial/parallel hardware implementation of the Berlekamp-Massey algorithm for BCH decoding in Flash controller applications

Error correction in Flash memories is often based on BCH codes and algebraic decoding that employs the Berlekamp-Massey-Algorithm (BMA) for solving the key equation. Commonly, hardware implementations of the BMA perform many Galois field multiplications in parallel. This guarantees a large throughput. Alternatively, serial implementations were proposed that require less logic but result in a much slower operation, in particular if the number of correctable errors is large. This paper presents a decoding technique that combines a serial and a parallel implementation to achieve a better trade-off between throughput and space complexity.

Set partitioning of Gaussian integer constellations and its application to two-dimensional interleaver design

This work demonstrates that the concept of set partitioning can be applied to Gaussian integer constellations that are isomorphic to two-dimensional modules over rings of integers modulo p. We derive upper bounds on the achievable minimum distance in the subsets and present a construction for the set partitioning. This construction achieves optimal or close to optimal minimum distances. Furthermore, we demonstrate that this set partitioning can be applied to an interleaving technique for correcting two-dimensional cyclic clusters of errors.

An efficient hardware implementation of sequential stack decoding of binary block codes

This work proposes an efficient hardware Implementation of sequential stack decoding of binary block codes. The decoder can be applied for soft input decoding for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used.

A Soft Input Decoder for High-rate Generalized Concatenated Codes

Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.