Jens Vygen

Algorithms for large-scale flat placement

This is a survey on the algorithms which are part ofa program for flat placement of large-scale VLSI processorchips. The basis is a quadratic optimization approachcombined with a new quadrisection algorithm.In contrast to most previous quadratic placement methods,no min-cut objective is used at all. Based on aquadratic placement, a completely new algorithm findsa four-way partitioning meeting capacity constraintsand minimizing the total movement.

Shorter tours by nicer ears: 7/5-Approximation for the graph-TSP, 3/2 for the path version, and 4/3 for two-edge-connected subgraphs

We prove new results for approximating the graph-TSP and some related problems. We obtain polynomial-time algorithms with improved approximation guarantees.For the graph-TSP itself, we improve the approximation ratio to 7=5. For a generalization, the minimum T-tour problem, we obtain the first nontrivial approximation algorithm, with ratio 3=2. This contains the s-t-path graph-TSP as a special case. Our approximation guarantee for finding a smallest 2-edge-connected spanning subgraph is 4=3.The key new ingredient of all our algorithms is a special kind of ear-decomposition optimized using forest representations of hypergraphs. The same methods also provide the lower bounds (arising from LP relaxations) that we use to deduce the approximation ratios.

NP-completeness of some edge-disjoint paths problems

Abstract We prove: The directed edge-disjoint paths problem is NP-complete, even if (a) the underlying graph G is acyclic, the demand graph H consists just of three sets of parallel edges and G + H is Eulerian, or (b) G + H is planar, or (c) G is planar and acyclic. (d) The undirected edge-disjoint paths problem is NP-complete, even if G + H is Eulerian and H consists just of three sets of parallel edges.

Cycle time and slack optimization for VLSI-chips

We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes all previously considered models. Then we show how to optimize the cycle time and optimally balance slacks on data paths and on clocktree paths. The problem of finding a clock schedule with the optimum cycle time was solved before, either by linear programming or by binary search, using a test for negative circuits in a digraph as a subroutine. We show for the first time that a direct combinatorial algorithm solves this problem optimally. Incidentally, this yields a new efficient method for timing analysis with transparent latches. Moreover, we extend this algorithm to the slack balancing problem: To make the chip less sensitive to routing detours, process variations and manufacturing skew it is desirable to have as few critical paths as possible. We show how to find the clock schedule with minimum number of critical paths (optimum slack distribution) in a well-defined sense. Rather than fixed dock arrival times we show how to obtain as large as possible intervals for the clock arrival times. This can be considered as slack on clocktree paths. Indeed, we can find the global optimum of simultaneous optimization of slacks on all data paths and clocktree paths. All the above is done by very efficient network optimization algorithms, based on parametric shortest paths. Our computational results with recent IBM processor chips show that the number of critical paths decreases dramatically, in addition to a considerable improvement of the cycle time. The running times are reasonable even for the largest designs.

The edge-disjoint path problem is NP-complete for series-parallel graphs

Abstract Many combinatorial problems are NP-complete for general graphs. However, when restricted to series–parallel graphs or partial k -trees, many of these problems can be solved in polynomial time, mostly in linear time. On the other hand, very few problems are known to be NP-complete for series–parallel graphs or partial k -trees. These include the subgraph isomorphism problem and the bandwidth problem. However, these problems are NP-complete even for trees. In this paper, we show that the edge-disjoint paths problem is NP-complete for series–parallel graphs and for partial 2-trees although the problem is trivial for trees and can be solved for outerplanar graphs in polynomial time.

Almost optimum placement legalization by minimum cost flow and dynamic programming

VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization).We consider algorithms for legalization. In particular, we analyze a generic legalization algorithm based on minimum cost flows and dynamic programming. Specializations are being used in industry for many years, and an improved version was proposed very recently in [2]. The objective of all these algorithms is to minimize the weighted sum of (squared) movements, i.e. they assume the placement to be already optimized except for not being legal.To evaluate results, we propose two different lower bounds for the legalization problem, one based on linear assignment, and the other one based on an integer linear programming relaxation. We prove that the second lower bound is always at least as good as the first one. We also show how to compute the bounds efficiently. We then give an extensive experimental analysis of the algorithms and the lower bounds by testing them on a set of recent industrial ASICs with up to 2.4 million cells. In particular, we show that the gap between the new algorithm and the better lower bound is usually less than 10 percent. This proves that the legalization problem is solved almost optimally.Besides (weighted) total (squared) movement, we also consider various other objectives like wirelength, timing, and routability. Our experiments demonstrate that minimizing total (weighted, squared) movement has almost no negative effect on the timing properties, routability and netlength. Therefore the new algorithm will help in overall design closure.

Clock Scheduling and Clocktree Construction for High Performance ASICS

In this paper we present a new method for clock schedulingand clocktree construction that improves the performance ofhigh-end ASICs significantly.First, we compute a clock schedule that yields the optimumcycle time and the best possible clock distribution with respectto early and late mode; in particular the number of criticaltests is minimized. Second, individual arrival time intervalsare computed for all endpoints of the clocktree. Finally, weconstruct a clocktree that realizes arrival times within theseintervals and exploits positive slacks to save power consumption.We demonstrate the superiority of our method to previousapproaches by experimental results on industrial ASICs withup to 194 000 registers and more than 160 clock domains. Weimproved the clock frequencies by 5-28% up to 1.033 GHz (in hardware).

Faster optimal single-row placement with fixed ordering

We consider the problem of placing a set of cells in a single row with a given horizontal ordering, minimizing the (weighted) bounding box netlength. We analyze the running time of an algorithm of Kahng, Tucker and Zelikovsky which solves this problem optimally. By using different data structures we are able to improve the worst-case running time in the unweighted case as well as in the presence of netweights.

Legalizing a placement with minimum total movement

Most tools for the placement of very large scale integrated chips work in two steps. First, the cells that have to be placed are roughly spread out over the chip area, ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization). In this paper, we describe new ideas for legalization. We divide the task into appropriate subproblems that can be solved optimality in polynomial time. For the most important parts, even a linear running time can be shown. Together, the solutions of the subproblems can be combined to an algorithm that legalizes a placement minimizing the total (linear or squared) movement of cells. The algorithm is tested on a set of recent application specific integrated circuits and the results are compared to lower bounds showing that it computes provably good solutions (within a few percent of the optimum) even on very large industrial chips. By introducing significantly fewer violations, our legalization helps in overall design closure.

Algorithms for detailed placement of standard cells

The state-of-the-art methods for the placement of large-scale standard cell designs work in a top-down fashion. After some iterations, where more and more detailed placement information is obtained, a final procedure for finding a legal placement is needed. This paper presents a new method for this final task, based on efficient algorithms from combinatorial optimization.