Stephan Held

Clock Scheduling and Clocktree Construction for High Performance ASICS

In this paper we present a new method for clock schedulingand clocktree construction that improves the performance ofhigh-end ASICs significantly.First, we compute a clock schedule that yields the optimumcycle time and the best possible clock distribution with respectto early and late mode; in particular the number of criticaltests is minimized. Second, individual arrival time intervalsare computed for all endpoints of the clocktree. Finally, weconstruct a clocktree that realizes arrival times within theseintervals and exploits positive slacks to save power consumption.We demonstrate the superiority of our method to previousapproaches by experimental results on industrial ASICs withup to 194 000 registers and more than 160 clock domains. Weimproved the clock frequencies by 5-28% up to 1.033 GHz (in hardware).

Maximum-weight stable sets and safe lower bounds for graph coloring

The best method known for determining lower bounds on the vertex coloring number of a graph is the linear-programming column-generation technique, where variables correspond to stable sets, first employed by Mehrotra and Trick in 1996. We present an implementation of the method that provides numerically-safe results, independent of the floating-point accuracy of linear-programming software. Our work includes an improved branch-and-bound algorithm for maximum-weight stable sets and a parallel branch-and-price framework for graph coloring. Computational results are presented on a collection of standard test instances, including the unsolved challenge problems created by David S. Johnson in 1989.

Efficient generation of short and fast repeater tree topologies

We present a very fast algorithm for topology generation of repeater trees. Based on the criticality of the individual sinks, which is estimated taking their required signal arrival times and their distance from the root of the repeater tree into account, this topology connects very critical sinks in such a way as to maximize the minimum slack and to minimize wiring for non-critical sinks.We establish theoretical bounds on the optimum solution and prove that our algorithm produces results that are close to optimum with respect to slack and wirelength. Experimental results on industrial designs in 130 nm and 90 nm technologies demonstrate the excellent quality of our algorithm. Moreover, one million nontrivial repeater tree topologies are constructed in less than one minute of computing time.

The repeater tree construction problem

A tree-like substructure on a computer chip whose task is to carry a signal from a source circuit to possibly many sink circuits and which consists only of wires and so-called repeater circuits is called a repeater tree. We present a mathematical formulation of the optimization problems related to the construction of such repeater trees. Furthermore, we prove theoretical properties of a simple iterative procedure for these problems which was successfully applied in practice.

Gate sizing for large cell-based designs

Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step. Slew targets are updated by an estimate of the local slew gradient. To demonstrate the effectiveness, we propose a new heuristic to estimate lower bounds for the worst path delay. On average, we violate these bounds by 6%. A subsequent local search decreases this gap quickly to 2%. This two-stage approach is capable of sizing designs with more than 5.8 million cells within 2.5 hours and thus helping to decrease turn-around times of multi-million cell designs.

Shallow-Light steiner arborescences with vertex delays

We consider the problem of constructing a Steiner arborescence broadcasting a signal from a root r to a set T of sinks in a metric space, with out-degrees of Steiner vertices restricted to 2. The arborescence must obey delay bounds for each r-t-path (t∈T), where the path delay is imposed by its total edge length and its inner vertices. We want to minimize the total length. Computing such arborescences is a central step in timing optimization of VLSI design where the problem is known as the repeater tree problem [1,5]. We prove that there is no constant factor approximation algorithm unless

Safe lower bounds for graph coloring

\mbox{\slshape P}=\mbox{\slshape NP}

Local search algorithms for timing-driven placement under arbitrary delay models

and develop a bicriteria approximation algorithm trading off signal speed (shallowness) and total length (lightness). The latter generalizes results of [8,3], which do not consider vertex delays. Finally, we demonstrate that the new algorithm improves existing algorithms on real world VLSI instances.

Post-Routing Latch Optimization for Timing Closure

The best known method for determining lower bounds on the vertex coloring number of a graph is the linear-programming columngeneration technique first employed by Mehrotra and Trick in 1996. We present an implementation of the method that provides numerically safe results, independent of the floating-point accuracy of linear-programming software. Our work includes an improved branch-and-bound algorithm for maximum-weight stable sets and a parallel branch-and-price framework for graph coloring. Computational results are presented on a collection of standard test instances, including the unsolved challenge problems created by David S. Johnson in 1989.

A fast algorithm for rectilinear steiner trees with length restrictions on obstacles

We present local search algorithms for timing-driven placement optimization. They find local slack optima for cells under arbitrary delay models and can be applied late in the design flow. The key ingredients are an implicit path straightening and a clustering of neighboring cells. Cell clusters are moved jointly to speed up the algorithm and escape suboptimal solutions, in which single cell algorithms are trapped, particularly in the presence of layer assignments. Given a cell cluster, we initially perform a line search for maximum slack on the straight line segment connecting the most critical upstream and downstream cells of the cluster. Thereby, the Euclidean path length is minimized. An iterative application will implicitly straighten the path. Later, slacks are improved further by applying ascent steps in estimated super-gradient direction. The benefit of our algorithms is demonstrated experimentally within an industrial microprocessor design flow, and on recent ICCAD benchmarks circuits.