Jeong-Gun Lee

Automatic process-oriented control circuit generation for asynchronous high-level synthesis

As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method, so called process-oriented method, which generates distributed asynchronous control circuits automatically in a hierarchical and systematic manner is suggested as part of an AHLS tool. Experimental results show that the suggested method is efficient in the aspects of area and performance of derived control circuits.

A parallel flop synchronizer for bridging asynchronous clock domains

Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data between clock domains. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed synchronization can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level.

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units

Nowadays, variable delay arithmetic units have been used for implementing a datapath of a target system in pursuit of performance improvement. However, adoption of variable delay arithmetic units requires modification of a typical synchronous control unit design methodology. A telescopic arithmetic unit based methodology is one of representative methodologies to design synchronous control units for variable delay datapaths. In this paper, we propose two optimization methods for it. Proposed optimization techniques will be analyzed in order to show their performance improvement effects explicitly.

Handshake-wave combined approach with runtime reconfiguration for designing a low latency asynchronous FIFO

In this paper, a novel design scheme combining a handshake protocol and wave pipeline is proposed to improve latency performance of an asynchronous linear FIFO. The stage control of the proposed FIFO can be reconfigured dynamically to be one of two different operating styles, waving or handshaking, according to the status of data flow in the FIFO. The use of wave pipelining in a control and a datapath can eliminate delays of handshaking circuits and latching data respectively. The proposed circuits have been designed with 0.25 /spl mu/m, 2.5 V CMOS process technology and simulated using HSPICE. Preliminary results show about two times improvement on latency performance over a state-of-art linear FIFO circuit while retaining throughput and a simple linear structure.

Imprecise data computation for high performance asynchronous processors

Instruction level parallelism(ILP) is strictly limited by various dependencies. In particular , data dependency is the major performance bottleneck of data intensive applications. To accelerate the execution of sequential code serialized due to data dependencies, this paper proposes an imprecise computation as a fast data computing technique for a high-performance asynchronous processor. To show the performance benefits of the suggested computing model, simulation results are presented. The imprecise computation can be used effectively in data intensive processing with a microprocessor, a Digital Signal Processor or a multimedia processor.

Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis

As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method to derive distributed asynchronous control circuits in an automatic and systematic manner is suggested as a part of an AHLS tool. In order to acquire control circuits with competent quality, a process-oriented method is proposed. Experimental results show that the suggested method is efficient in the aspects of area and performance of the derived control circuits.

Instruction level redundant number computations for fast data intensive processing in asynchronous processors

Instruction level parallelism (ILP) is strictly limited by various dependencies. In particular, data dependency is a major performance bottleneck of data intensive applications. In this paper we address acceleration of the execution of instruction codes serialized by data dependencies. We propose a new computer architecture supporting a redundant number computation at the instruction level. To design and implement the scheme, an extended data-path and additional instructions are also proposed. The architectural exploitation of instruction level redundant number computations (IL-RNC) makes it possible to eliminate carry propagations. As a result execution of instructions which are serialized due to inherent data dependencies is accelerated. Simulations have been performed with data intensive processing benchmarks and the proposed architecture shows about a 1.2-1.35 fold speedup over a conventional counterpart. The proposed architecture model can be used effectively for data intensive processing in a microprocessor, a digital signal processor and a multimedia processor.

Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization

Asynchronous circuit design is very attractive as a high performance design method since it can achieve average-case delay. However, it is hard to make use of such an advantage in a pipelined architecture due to the blocking/starvation effects between stages. In most of current solutions, buffers are allocated to reduce the blocking/starvation effects but it is difficult to find a distribution of buffers over an asynchronous linear pipeline(ALP) that is optimal in terms of ‘time*area’ cost.

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units

In order to enjoy the performance improvement effects of variable computation time arithmetic units at a system level, we propose a new synchronous control unit design methodology for dataflow graphs under allocation of a telescopic arithmetic unit, which is one of the well-known synchronous variable computation time arithmetic units. The proposed method generates an independent synchronous controller for each component arithmetic unit, and builds a distributed synchronous control unit through integrating the derived controllers. The distributed structure of the final synchronous control unit maximizes the performance improvement effect of telescopic arithmetic units through a complete preservation of original concurrency among operations.

Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.