Euiseok Kim

A zero-time-overhead asynchronous four-phase controller

Asynchronous single-rail datapath implementations turn out to be superior to the dual-rail implementations in some dimensions; they consume less energy and require less circuit area. However, there still exist area overhead of matched delay elements and control time overhead of the four-phase handshake protocol. In this paper, we introduce a new interface so that such time overhead can be reused as a part of the matched delay. Consequently, the time overhead can be zero, and the amount of components used for composing the matched delay can be dramatically reduced. The larger the control time overhead is, the smaller the delay chain becomes. The full performance and low-power advantages of asynchronous circuits can be obtained. We demonstrate this on a single-rail differential equation solver.

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units

Nowadays, variable delay arithmetic units have been used for implementing a datapath of a target system in pursuit of performance improvement. However, adoption of variable delay arithmetic units requires modification of a typical synchronous control unit design methodology. A telescopic arithmetic unit based methodology is one of representative methodologies to design synchronous control units for variable delay datapaths. In this paper, we propose two optimization methods for it. Proposed optimization techniques will be analyzed in order to show their performance improvement effects explicitly.

Imprecise data computation for high performance asynchronous processors

Instruction level parallelism(ILP) is strictly limited by various dependencies. In particular , data dependency is the major performance bottleneck of data intensive applications. To accelerate the execution of sequential code serialized due to data dependencies, this paper proposes an imprecise computation as a fast data computing technique for a high-performance asynchronous processor. To show the performance benefits of the suggested computing model, simulation results are presented. The imprecise computation can be used effectively in data intensive processing with a microprocessor, a Digital Signal Processor or a multimedia processor.

Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis

As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method to derive distributed asynchronous control circuits in an automatic and systematic manner is suggested as a part of an AHLS tool. In order to acquire control circuits with competent quality, a process-oriented method is proposed. Experimental results show that the suggested method is efficient in the aspects of area and performance of the derived control circuits.

A new resource constrained asynchronous scheduling method through transformation of dataflow graphs

With the increase of popularity in an asynchronous system design style, the request for asynchronous high-level synthesis tools is increasing continuously. In this paper, we suggest a new resource constrained asynchronous scheduling method which is performed through transformation of a dataflow graph (DFG). Experimental results show that the suggested scheduling method can produce a correct and efficient schedule from an initial DFG and the resulting schedule leads to a faster and more flexible asynchronous system compared to a corresponding synchronous system.

Control signal sharing using data-path delay information at control data flow graph descriptions

Due to the state explosion problem, signal transition graph based asynchronous circuit synthesis cannot handle large specifications. To overcome this problem, we propose two control signal sharing methods by using the delay information of data-path circuit. Since the number of states is exponential with the number of signals in the synthesis, the reduction of signals by sharing can reduce the number of states in exponential order. They are carried out at the control of data path operations which is represented as a control flow graph description, without sacrificing the critical path delay of the data-path circuit. Experimental results are encouraging in that a number of control signals can be shared by our methods.

Control signal sharing of asynchronous circuits using datapath delay information

Due to state explosion problem in synthesis, most of asynchronous CAD tools based on graph models cannot handle large specifications. To overcome this problem, in this paper, we propose two control signal sharing methods by using the delay information of datapath circuits. The reductions of signals by sharing reduce the number of states significantly and result in area optimal circuits. They are carried out at control flow graph (CFG) descriptions in terms of node sharing. Experimental results are encouraging in that a number of control signals are shared.

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units

In order to enjoy the performance improvement effects of variable computation time arithmetic units at a system level, we propose a new synchronous control unit design methodology for dataflow graphs under allocation of a telescopic arithmetic unit, which is one of the well-known synchronous variable computation time arithmetic units. The proposed method generates an independent synchronous controller for each component arithmetic unit, and builds a distributed synchronous control unit through integrating the derived controllers. The distributed structure of the final synchronous control unit maximizes the performance improvement effect of telescopic arithmetic units through a complete preservation of original concurrency among operations.

Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.