Jeong-Lim Nam

Mechanisms of stress-induced voids in multi-level Cu interconnects

One of the most serious problems in Cu-based multilevel integration is the failure in stacked vias caused by stress-induced voids. In this paper, the failure mechanism of the stacked via resistance is evaluated by analyzing the effects of the conditions of deposition and annealing in electroplated-Cu (EP-Cu) and the damascene structure scheme in a 64-bit RISC microprocessor with 7 copper layers. The stress-induced void is closely related to the stress change and the volume shrinkage of EP-Cu generated during deposition and annealing. The stacked via failures can be effectively suppressed with the application of two-step deposition and annealing in the EP-Cu process at the relatively low temperature of about 200/spl deg/C and the single damascene scheme for the layer of Via-5/Metal-6.

Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology

An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.

Improved overlay measurement of CMP processed layers

We report the results of an investigation into the quality of overlay data obtained from a chemical-mechanical polish (CMP) process. The limiting step height for standard bright field optical imaging is examined and found to be less than 200 angstrom. Tool repeatability improvements are demonstrated using a mixture of imaging system modifications and image processing techniques. Using these it is possible to achieve very repeatable data. Good tool precision is insufficient evidence of good data quality as the process can distort the target so that it does not accurately measure the stepper overlay error. We report an examination of data quality obtained using different target designs and both with and without an additional etch- back step to enhance the contrast of the image being measured. Several different techniques have been applied to determine whether the data is accurate. We conclude that bar and frame type targets give much more accurate results than traditional box styles. In addition the tool performance is also improved by using the same target designs. With this choice of target design accurate data is obtained and meaningful correction of stepper errors becomes possible.

Control of resist flow process for sub-0.15-μm small contact hole by latent image

Bake process of photo resist above glass transition temperature (Tg) increases its fluidity and shrinks contact holes patterned on the wafer. This process enables us to define sub-0.2 micrometers contact hole pattern with KrF, which is one of major issues of sub-0.15 micrometers device technology. However, the amount of PR flow depends on the contact hole size, pattern density and environment, which makes it difficult to control the fine critical dimension (CD) variation. In this paper, new approach to overcome the difficulties is studied with acetal type PR and attenuated phase shift mask (att. PSM). It is found that the change of chemical bonding in PR by light exposure decreases the resist flow sensitivity, which makes us solve the problems. The att. PSM enables us to control the aerial image intensity between contact holes, and the CD variation induced by bake process was drastically decreased when it is compared to Cr mask. The layout optimization by simulation for aerial image control in bulk region, and the resist flow process combined with att. PSM allows us to control the CD variation less than 20 nm for the sub-0.15 micrometers devices fabrication.

Effects of illumination wavelength on the accuracy of optical overlay metrology

As the integration density in the manufacturing of ICs increases and tighter design rules are implemented, the accuracy of overlay in the photolithography process is becoming all the more important. Consequently, investigation and characterization of the accuracy (as well as precision) of the overlay measurement are being required to insure that the overlay metrology tool qualifies for the new technologies. In this paper, we analyze the relationship between wafer substrate types and the respective characteristic overlay measurement errors associated with them. We compare results using different illumination wavelengths in the overlay tool. We define the Wafer Induced Shift (WIS) contribution to the measurement accuracy error and introduce a metric for it. And we analyze the relationship between the TIS and WIS. We show that the wavelength of the optical overlay measurement (OL, for short) should be fitted separately to each of the various kinds of overlay measurement targets, or marks. Buried type targets, covered by transparent materials, for which the measurement is made through the transparent interlayer, benefit from wavelength selection due to the possible improvement in contrast associated with an interference effect. Open type targets, on the other hand, in which the measurement signal is collected off the substrate shape itself, do not benefit from that. There is another problem to consider, however. Such targets may show a considerable WIS, even thought TIS and precision are good both before and after etch. The WIS error can be as high as 100 nm. This could create serious OL problem and it means that TIS and precision are not enough to characterize the quality of measurement, and WIS is equally important, it not more so. We look into the causes of WIS in the substrate shape, overlay mark design and fabrication method. We show that with careful selection of illumination wavelength, some layers produce no WIS. On the other layers WIS remains a problem and other methods are still required to control it.

Pattern deformation induced from intensity-unbalanced off-axis illumination

Currently it is very popular to use off-axis illumination technique for higher resolution with wider depth of focus. However there are several problems in the technique, one of which is deterioration of image quality induced by the non- uniform effective source distribution. If the intensity distribution on the illumination aperture lacks of spatial symmetry, each diffraction order beam impinging on the wafer surface has angularly asymmetric distribution. This makes the optical system have pattern size dependent telecentricity error. For a simple line or grouped lines it gives rise to only the pattern displacement with defocus which can hardly be detected unless there are any reference. But the periodic island type patterns which have discrete features and multiple pitch components in one direction can be bent and deformed asymmetrically with defocus. Asymmetric imaging for island type patterns gives rise to also the pattern CD asymmetry with defocus. We present schematic explanation of the effects of non-uniform effective source and the simulation result. We also investigated the phenomena in a high density DRAM cell active layer of 460 nm minimum pitch and characterized it by various approach.

Method for prevention of unopened contact hole in dual-damascene process

In spite of the advantages of low cost and resistance, dual damascene process has some problems. When contact holes are patterned within the trench patterns, the contact holes are frequently found to be unopen and are bent toward trench side wall (TSW). These cause CD variation and small depth of focus. We can explain this phenomenon in view of limited resolution of photoresist (PR) and the light reflected from the TSW. The deeper the trench depth is, the thicker the thickness of the photoresist for contact hole patterns is, which leads to decreased resolution. And the light reflected off the TSW makes the contact holes profile bent toward TSW. This reflected light influences on both sides. One is helpful in defining the contact holes near the TSW, and the other causes CD variations according to distance between the contact holes and TSW. If the contact holes and trench patterns are exactly the same sizes, it is possible to decrease the CD variation and to prevent PR contact holes from unopening within the trench patterns. Also it is of help to improve resolution at the bottom of the PR.

Mechanism of deep-UV photoresist tail on inorganic antireflective layer film

As the minimum feature size decreases down to 0.20micrometers , a minute pattern deformation can result in serious critical dimension variation. To minimize the critical dimension variation, the interaction of the positive-tone chemical amplification resist with SiOxNy type inorganic anti-reflective layer is investigated. The surface characterization of inorganic anti-reflective layer reveals that Si-NHx(x=0,1,2) and Si-N=O groups are attributed to the cause of the DUV PR footing. Based on the analyses, the technique to reduce the pattern deformation of the chemical amplification resist on inorganic anti-reflective layer is suggested.

Influence of intermetal dielectric thickness on overlay mark size variation in photolithography

The pattern size variation (PSV) and pattern size deviation (PSD) dependency on inter-metal dielectrics (IMD) thickness is studied to improve overlay performance. A new model is introduced to explain the cause of such a large PSD and PSV(> 1 micrometer), which are frequently encountered in real process followed by chemical mechanical polishing (CMP) process. Abnormal PSD depends more on focus and substrate structure than on dose. The IMD as thick as 4 micrometer gives rise to a large PSD by 1 micrometer for a 3 micrometer overlay mark. To solve such large PSD and PSV, two solutions are suggested: application of anti-reflective layer (ARL) beneath the IMD or placement of a reflective layer in the middle of IMD. With this improvement, the failure rate of the overlay mark detection decreased from approximately 90% to less than approximately 2%.

Improved overlay reading on MLR structures

In this paper, we present methods of eliminating an overlay scaling error which is introduced when multi-layer resist (MLR) structures are imaged with a narrow bandwidth light source. Using the conventional box-in-box type mark, an intense interference fringe is produced around the box type mark and results in a scaling error on overlay reading. An optical interference effect combined with resist build-up of bottom PR is the origin of the scale error. Two methods have been tried to find a solution without changing the process. To remove the interference effects, a broad bandwidth light source was adopted so that clean and uniform images are obtained. On the other hand, to eliminate the resist build-up, narrow bar marks corresponding to the large box pattern have been generated to reduce the effect with the narrow bandwidth light source. Using the above methods we could realize accurate overlay measurement on MLR structures. The changes have been applied to a real DRAM process.