Sang-rok Hah

Effects of nonionic surfactants on oxide-to-polysilicon selectivity during chemical mechanical polishing

The effects of surfactants on oxide-to-polysilicon selectivity during chemical mechanical polishing have been investigated. Slurries with nonionic surfactants such as Brij surfactants, polyethylene oxide (PEO), and ethylene oxide-propylene oxide-ethylene oxide triblock copolymer enhanced oxide-to-polysilicon polishing selectivity. Although a current conventional oxide slurry has a low oxide-to-polysilicon selectivity of 0.5:1, slurries with nonionic surfactants show a higher selectivity due to a combined effect of adsorption and interfacial adhesion of added nonionic surfactant molecules on the polysilicon surface. The oxide-to-polysilicon selectivity of the Brij surfactant added slurry displayed a stronger dependency on the hydrophile-lipophile-balance (HLB) value than the type of alkyl group or the chain length of surfactants. Especially, Brij52 with low HLB value gave an oxide-to-polysilicon selectivity of 9.3, which is 17 times higher than the selectivity of a commercial oxide slurry. A high molecular weight polymeric surfactant such as PEO also gave a greater selectivity than a low molecular weight surfactant. In addition, slurries with nonionic surfactants reduce the final thickness variation effectively in damascene structure having a polysilicon stopping layer. The final thickness variation polished with the Brij52 added slurry was decreased to one fourth of that with the conventional oxide slurry only.

Mechanisms of stress-induced voids in multi-level Cu interconnects

One of the most serious problems in Cu-based multilevel integration is the failure in stacked vias caused by stress-induced voids. In this paper, the failure mechanism of the stacked via resistance is evaluated by analyzing the effects of the conditions of deposition and annealing in electroplated-Cu (EP-Cu) and the damascene structure scheme in a 64-bit RISC microprocessor with 7 copper layers. The stress-induced void is closely related to the stress change and the volume shrinkage of EP-Cu generated during deposition and annealing. The stacked via failures can be effectively suppressed with the application of two-step deposition and annealing in the EP-Cu process at the relatively low temperature of about 200/spl deg/C and the single damascene scheme for the layer of Via-5/Metal-6.

A Highly Reliable Cu Interconnect Technology for Memory Device

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.

Effect of Polish By-Products on Copper Chemical Mechanical Polishing Behavior

The stains on the pad caused by polishing by-products can be observed in a copper chemical and mechanical polishing (CMP) process. In this study, the effects of stains on CMP performance such as erosion, dishing, and nonuniformity were evaluated as a function of the degree of stains accumulated on the pad. The stains on the pad deteriorate the nonuniformity of removal rate and result in the increase in erosion and dishing. CMP by-products adhere on both pores and grooves of the pad and block the flow of slurry through the grooves, resulting in the deterioration of nonuniformity. The selectivity (ratio of removal rate, Cu to TaN or dielectric film) is important in order to minimize erosion. When wafers were polished on a stained pad, the removal rate of Cu decreased ∼ 30% due to the poor slurry distribution and the selectivity decreased more than 40% because the mechanical abrasion was enhanced by the presence of by-products on pad surfaces. The lower the selectivity, the higher the level of erosion on the polished patterned wafers. The higher frictional force on a stained pad results in higher temperature and etch rate of Cu which might be the reason for recess and dishing of Cu lines.

A Planarization Model in Chemical Mechanical Polishing of Silicon Oxide using High Selective CeO 2 Slurry

This paper attempts to establish planarization model in chemical mechanical polishing of silicon oxide using high selective ceria slurry. Though removal rate of the high area is increased due to a high pressure focused on the area with abrasive and pad, the removal rate of the same area is not increased but decreased even in the very beginning of polishing with ceria slurry. It also observed that only the elevated area is polished and dishing is not occurred during the polishing in high selective ceria CMP. In this work, it is proposed that ceria abrasives are filled in the low trench area and then support the pad as well as high area during the CMP, which results in planarization without dishing.

Electrical characterization of contact level PVC (Passive Voltage Contrast) test using a nanoprober

PVC (Passive Voltage Contrast) fault isolation method by using a SEM (Scanning Electron Microscope) has been widely used for isolating the defective mc (metal contact) in the CMOS logic SRAM bit cell array. The low power (LP) processed sram cells are easy to charging under PVC test and it helps isolating defective contacts in the cell. However, some device such as a high speed (HS) sram cell is hard to charging in PVC test by unknown reason. It makes difficulties for isolating defective contacts in the sram cell array. In this paper, our group analyzed the electrical current of each contact in sram cell using a nanoprobing technique and correlated it with PVC charged contact images, respectively. Also, the difference of PVC charging status between LP and HS SRAM are characterized electrically by using a nanoprober. The nanoprobing result indicates that a slight increasing a leakage current of about 10pA can abruptly change the charging brightness from dark to grey. Finally, we can found some clues for making grey contacts of HS SRAM using not only a nanoprobing but also a HRTEM (High Resolution Transmission Electron Microscope) image.

A Study of the Planarity by Sti Cmp Erosion Modeling

In this work, we propose a new equation that predicts the planarity as a function of active pattern density, initial step height, selectivity between gapfilled oxide and silicon nitride and over CMP amounts. In order to achieve highly planarized STI surface, uniform active density, reduced initial step height, minimization of over CMP amounts and high selective slurry were required. Our new equation was applied to the 0.18um graded CPU devices’ STI CMP to enhance planarity and these parameters were evaluated quantitatively. It is concluded that the model suggested is useful in predicting CMP planarity

The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnects

The effect of FSG film properties as inter-metal dielectrics on stress-induced voiding (SIV) phenomena in Cu dual-damascene interconnects has been investigated with various FSG-films. HDPFSG and PEFSG2 showed less SIV failure than those of PEFSGI and 3. These behaviors of SIV according to FSG films agree well with desorbed amount of hydrogen, oxygen and fluorine ions from FSG films at high temperature over 400/spl deg/C. The result of SIMS analysis suggests that SIV phenomena are improved by application of stable FSG film without desorption at high temperature such as HDPFSG and PEFSG2 used in this work.