Jeong Soo Park

T&I engine: traversal and intersection engine for hardware accelerated ray tracing

Ray tracing naturally supports high-quality global illumination effects, but it is computationally costly. Traversal and intersection operations dominate the computation of ray tracing. To accelerate these two operations, we propose a hardware architecture integrating three novel approaches. First, we present an ordered depth-first layout and a traversal architecture using this layout to reduce the required memory bandwidth. Second, we propose a three-phase ray-triangle intersection architecture that takes advantage of early exit. Third, we propose a latency hiding architecture defined as the ray accumulation unit. Cycle-accurate simulation results indicate our architecture can achieve interactive distributed ray tracing.

HART: A Hybrid Architecture for Ray Tracing Animated Scenes

We present a hybrid architecture, inspired by asynchronous BVH construction [1], for ray tracing animated scenes. Our hybrid architecture utilizes heterogeneous hardware resources: dedicated ray-tracing hardware for BVH updates and ray traversal and a CPU for BVH reconstruction. We also present a traversal scheme using a primitives axis-aligned bounding box (PrimAABB). This scheme reduces ray-primitive intersection tests by reusing existing BVH traversal units and the primAABB data for tree updates; it enables the use of shallow trees to reduce tree build times, tree sizes, and bus bandwidth requirements. Furthermore, we present a cache scheme that exploits consecutive memory access by reusing data in an L1 cache block. We perform cycle-accurate simulations to verify our architecture, and the simulation results indicate that the proposed architecture can achieve real-time Whitted ray tracing animated scenes at 1,920 × 1,200 resolution. This result comes from our high-performance hardware architecture and minimized resource requirements for tree updates.

A randomized controlled trial comparing Laryngeal Mask Airway removal during adequate anesthesia and after awakening in children aged 2 to 6 years.

STUDY OBJECTIVEnTo compare the frequency of airway complications during removal of the Laryngeal Mask Airway (LMA) in 2 to 6 year old pediatric patients.nnnDESIGNnProspective randomized study.nnnSETTINGnOperating room at a university hospital.nnnPATIENTSn92 ASA physical status 1 and 2 pediatric patients, aged 2 to 6 years.nnnINTERVENTIONSnParticipants were randomized to two groups: anesthesia state (anesthesia group) and awake state (awake group). Anesthesia was induced and maintained with sevoflurane. Patients were allowed to maintain spontaneous respiration. In the anesthesia group, the LMA was removed during anesthesia with 2.2% of sevoflurane. In the awake group, the LMA was removed when patients met the recovery criteria, including facial grimace, spontaneous eye opening, and purposeful arm movement.nnnMEASUREMENTSnDuring and after removal of the LMA, the frequencies of airway-related complications including cough, severe salivation, LMA biting or teeth clenching, breath holding, laryngospasm, desaturation (SpO(2) < 95%), and vomiting, were recorded. The frequencies of upper airway obstruction and duration of emergence from anesthesia also were compared.nnnMAIN RESULTSnThe frequency of airway-related complications was significantly less in the anesthesia group than the awake group (4.8% vs 37.2%, P = 0.001). Of the complications, cough, desaturation, excessive secretion, and LMA biting were less common in the anesthesia group. No differences between groups were noted in the frequency of upper airway obstruction and duration of emergence from anesthesia.nnnCONCLUSIONnIn 2 to 6 year old pediatric patients, an adequate anesthetic state is preferable to the awake state during LMA removal, producing fewer complications.

An FPGA implementation of whitted-style ray tracing accelerator

This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.

Ordered depth-first layouts for ray tracing

We present an ordered depth-first tree layout for ray tracing. Among two child nodes, a child node with the larger surface area is stored next to its parent node. Hence, the probabilities that a ray accesses to the same cache line increase. Our approach can be easily and widely used for various ray tracing systems with very small overheads, as it is based on existing depth-first layouts.

The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing

We propose effective texture-mapping hardware for real-time ray tracing. Therefore, we introduce a novel method to select the MIP-map level of texture images, which requires only the total length of the intersected ray and the pre-calculated value. The proposed architecture can support the texture MIP-mapping by integrating simple hardware logic in existing ray-tracing hardware.

An effective depth data memory system using an escape count buffer for 3D rendering processors

This paper proposes an effective memory system of depth data to reduce the bandwidth requirement from the external memory for low-power 3D rendering processors. For this purpose, we propose an escape count buffer that contains information about the data size for each compressed depth block. Compared to the previous scheme, experimental results show that this approach reduces the memory bandwidth requirements up to 44%.

Node pre-fetching architecture for real-time ray tracing

The traversal process in accelerated ray tracing algorithms requires many memory transactions of an acceleration structure. We present a pre-fetching system to pre-load potential node data into a cache. Experimental results show that the proposed scheme increases the performance of a cache system by reducing the cache miss rate.