Jer Min Jou

Design of low-error fixed-width multipliers for DSP applications

In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and twos-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2 n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low error reduced-width multiplier with output bit-width between n- and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.

Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme

In this paper, two efficient VLSI architectures for the biorthogonal wavelet transform are proposed. One is constructed by the filter bank implementation and another is constructed by the lifting scheme. In the filter bank implementation, due to the symmetric property of the biorthogonal wavelet transform, the proposed architecture uses fewer multipliers than the orthogonal wavelet transform. We also adopt the polyphase decomposition to speed up the processing by a factor of 2. In the lifting scheme implementation, the pipeline design style is adopted to optimise the architecture. Both of the proposed VLSI architectures have advantages of lower implementation complexity, faster computation time, and the inverse DWT has the same architecture as the forward DWT. Finally, the architecture constructed by the lifting scheme is implemented in a single chip on a 0.35 /spl mu/m 1P4M CMOS technology, and its area and working performance are 5.005/spl times/5.005 mm/sup 2/ and 50 MHz, respectively.

The gray prediction search algorithm for block motion estimation

Due to the temporal and spatial correlation of the image sequence, the motion vector of a block is highly related to the motion vectors of its adjacent blocks in the same image frame. If we can obtain useful and enough information from the adjacent motion vectors, the total number of search points used to find the motion vector of the block may be reduced significantly. Using that idea, an efficient gray prediction search (GPS) algorithm for block motion estimation is proposed in this paper. Based on the gray system theory, the GPS can determine the motion vectors of image blocks quickly and correctly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as 3SS, CS, PHODS, 4SS, BBGDS, SES and PSA, in terms of six different measures: (1) average mean square error per pixel; (2) average peak signal-to-noise ratio; (3) average prediction errors per pixel; (4) average entropy of prediction errors; (5) average percentage of unpredictable pels per frame; and (6) average search points per block.

An adaptive fuzzy logic controller: its VLSI architecture and applications

Most previous work about the hardware design of a fuzzy logic controller (FLC) intended to either improve its inference performance for real-time applications or to reduce its hardware cost. To our knowledge, there has been no attempt to design a hardware FLC that can perform an adaptive fuzzy inference for the applications of on-line adaptation. The purpose of this paper is to present such an adaptive memory-efficient FLC and its applications. Taking advantage of the adaptability provided by a symbolic fuzzy rule format and the dynamic membership function generator, as well as the high-speed integration capability afforded by VLSI, the proposed adaptive fuzzy logic controller (AFLC) can perform an adaptive fuzzy inference process using various inference parameters, such as the shape and location of a membership function, dynamically and quickly. Three examples are used to illustrate its applications, and the experimental results show the excellent adaptability provided by AFLC.

Dynamic pipeline design of an adaptive binary arithmetic coder

Arithmetic coding is an attractive technique for lossless data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a lower-area but faster fixed-width multiplier are applied, which implement the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8-/spl mu/m SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential realisation is achieved.

Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs

Networks-on-a-chip (NoC) is a new architectural template, which helps to meet many of challenges of designing a complex system-on-a-chip (SoC). In the paper, we introduce the on-chip network of and propose the dual-mode router for NoC which provides both guaranteed and best-effort communication services. We adopt the recording table for circuit switching to support the guaranteed service, and in order to sufficiently utilize the bandwidth of the network we add the wormhole switching which contains several virtual channels. Additionally, our router integrates the standard interface with AMBA AHB for easier integration of the intellectual properties (IPs) of NoC. The benchmark router with 5 32-bit ports can operate at 100 MHz and the bandwidth per link of the router can be up to 3.2 Gbps. The performance of the router is enough for providing an HDTV application on NoC.

A high-speed and decentralized arbiter design for NoC

As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and Decentralized Round-robin Arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters, the HDRA design, based on a de-centralized structure, is fast with only O(log4N) in critical path delay, area-efficient, and fair. The design results of it show that the arbitration performance of the HDRA is best compared with all existing arbiters, and still has smaller area cost. This new arbiter is being applied for a patent of the ROC (application No.: 0971xxxxx).

A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)

In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.

Adaptive arithmetic coding using fuzzy reasoning and grey prediction

Abstract Arithmetic coding is an attractive technique for lossless data compression. The most important thing in arithmetic coding is to construct a good modeler that always provides accurate probability estimation for incoming data. However, the characteristics of various types of source data bear a lot of uncertainty and are hard to be extracted, so we integrate fuzzy logic and grey theory to develop a smart fuzzy-grey-tuning modeler to deal with the problem of probability estimation. The average compression efficiency of the proposed method is better than other lossless compression methods, such as the Huffman, the approximate arithmetic, and the Lempel–Ziv, for three types of source data: text files, image files and binary files. Besides, the design is simple, fast, and suitable for VLSI implementation since an efficient table-look-up approach is adopted.

A fast-search motion estimation method and its VLSI architecture

An efficient search algorithm for block motion estimation is proposed in this paper. By using fuzzy reasoning, the algorithm can determine the motion vectors of image blocks quickly and correctly. Our experimental results show that the proposed algorithm performs better than other search algorithms, such as 3SS, CS, PHODS, 4SS, BBGDS, SES, PSA, and GPS. The VLSI architecture of the algorithm has been developed, and in simulation it yields a search rate of 683 000 blocks/s with a clock rate of 66 MHz.