Yeu Horng Shiau

Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme

In this paper, two efficient VLSI architectures for the biorthogonal wavelet transform are proposed. One is constructed by the filter bank implementation and another is constructed by the lifting scheme. In the filter bank implementation, due to the symmetric property of the biorthogonal wavelet transform, the proposed architecture uses fewer multipliers than the orthogonal wavelet transform. We also adopt the polyphase decomposition to speed up the processing by a factor of 2. In the lifting scheme implementation, the pipeline design style is adopted to optimise the architecture. Both of the proposed VLSI architectures have advantages of lower implementation complexity, faster computation time, and the inverse DWT has the same architecture as the forward DWT. Finally, the architecture constructed by the lifting scheme is implemented in a single chip on a 0.35 /spl mu/m 1P4M CMOS technology, and its area and working performance are 5.005/spl times/5.005 mm/sup 2/ and 50 MHz, respectively.

Low Complexity Underwater Image Enhancement Based on Dark Channel Prior

Blurred underwater image is always an annoying problem in the oceanic engineering. In this paper, we propose an efficient and low complexity underwater image enhancement method based on dark channel prior. Our method employs the median filter instead of the soft matting procedure to estimate the depth map of image. Moreover, a color correction method is adopted to enhance the color contrast for underwater image. The experimental results show that the proposed approach can effectively enhance the underwater image and reduce the execution time. Besides, this method requires less computing resource and is well suitable for implementing on the surveillance and underwater navigation in real time.

Hardware Implementation of a Fast and Efficient Haze Removal Method

In this letter, a fast and efficient haze removal method is presented. We employ an extremum approximate method to extract the atmospheric light and propose a contour preserving estimation to obtain the transmission by using edge-preserving and mean filters alternately. Our method can efficiently avoid the halo artifact generated in the recovered image. To meet the requirement of real-time applications, an 11-stage pipelined hardware architecture for our haze removal method is presented. It can achieve 200 MHz with 12.8 K gate counts by using TSMC 0.13- μm technology. Simulation results indicate that our design can obtain comparable results with the least execution time compared to previous algorithms and is suitable for low-cost high-performance hardware implementation for haze removal.

A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images

Wide-angle cameras are widely used in surveillance and medical imaging applications nowadays. Images captured by wide-angle lens suffer from barrel distortion which means that the outer regions of the image are compressed more than the inner one. A low-cost high-speed VLSI implementation for barrel distortion correction is presented in this brief. In our simulation, the proposed circuit can achieve 200 MHz with 45 K gate counts by using TSMC 0.18 mum technology. Compared with the previous distortion correction design, our circuit requires less hardware cost and achieves faster working speed.

Dynamic pipeline design of an adaptive binary arithmetic coder

Arithmetic coding is an attractive technique for lossless data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a lower-area but faster fixed-width multiplier are applied, which implement the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8-/spl mu/m SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential realisation is achieved.

A low-cost Gray prediction search chip for motion estimation

Taking advantage of the prediction ability provided by Gray system theory, the Gray prediction search (GrPS) algorithm can determine the motion vectors of image blocks correctly and quickly. A dedicated GrPS chip, which is with low cost and has the properties of regular-data-flow computations, is proposed in this paper to support the MPEG video resolution in real time. With 0.6-/spl mu/m CMOS technology, the proposed chip needs a die size of 2.8/spl times/2.9 mm/sup 2/ with about 54-K transistors, and can work with a clock rate of 66 MHz. Since GrPS performs better than other fast search algorithms, such as TSS, CS, PHODS, FSS, and SES, this low-cost GrPS chip is a good candidate for real-time motion estimation.

A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications

For real-time surveillance and safety applications in intelligent transportation systems, high-speed processing for image enhancement is necessary and must be considered. In this paper, we propose a fast and efficient illumination adjustment algorithm that is suitable for low-cost very large scale integration implementation. Experimental results show that the proposed method requires the least number of operations and achieves comparable visual quality as compared with previous techniques. To further meet the requirement of real-time image/video applications, the 16-stage pipelined hardware architecture of our method is implemented as an intellectual property core. Our design yields a processing rate of about 200 MHz by using TSMC 0.13-μm technology. Since it can process one pixel per clock cycle, for an image with a resolution of QSXGA (2560 × 2048) , it requires about 27 ms to process one frame that is suitable for real-time applications. In some low-cost intelligent imaging systems, the processing rate can be slowed down, and our hardware core can run at very low power consumption.

High Dynamic Range Image Rendering with Order-Statistics Filter

In this paper, we propose an efficient algorithm for dynamic range compression that is able to obtain high-quality results with low computational cost and without halo artifact. the approach belongs to the category of methods based on the Retinex theory. an edge-preserving filter based on the concept of order-statistics filter is presented for the estimation of the illumination. the experimental results show that our approach can effectively compress the HDR image for varied conditions.

An efficient VLSI architecture for convolutional code decoding

In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.

A novel motion estimation algorithm and its VLSI architecture

This paper presents a new motion estimation algorithm for the video coding, which combines the motion fuzzy prediction. our previous research, and modified four-step search algorithm (4SS) to reach faster and more correct searching results. Besides, its VLSI architecture is also proposed and implemented. With the analysis of the relationship between the consecutive search iterations, some of the searching operation are saved which enhance the computing efficiency and reduce power consumption. Experitncntal results demonstrate the higher performance in both PNSR and computation complexity then other motion estimation systems.