Jer-shen Maa

Characterization and reduction of twist in Ge on insulator produced by localized liquid phase epitaxy

Conditions for producing high-quality localized Ge-on-insulator film stacks on Si substrates by liquid phase epitaxy are discussed. In particular, we have found that the resulting Ge crystal planes have a tendency to exhibit a twist about the long axis of the crystal. If the wafer is heated much above the Ge melting temperature, this twist can be quite large (∼10°). The twist can be minimized by heating to just above the melting temperature and by using thicker Ge films. In spite of this twist, the Ge regions on top of the insulating Si3N4 are observed to be free of dislocations and stacking faults.

Effect of interlayer on thermal stability of nickel silicide

The thermal stability of nickel silicide is improved significantly by adding a thin layer of Ir or Co at the Ni/Si interface. The sheet resistance remains low after 850 °C annealing. The thermal stability was evaluated by measuring the junction leakage of an ultra-shallow junction with a 40 nm junction depth. With Ir, the film was stable and the reverse leakage of both N+/P and P+/N junctions remained in the picoampere range at 3 V on 100 μm×100 μm feature after 850 °C annealing. With Co, the leakage from P+/N junctions was low when the temperature was as high as 850 °C; leakage from N+/P junction was in the picoampere range up to 750 °C. These films were characterized by x-ray diffraction. The improved stability and low junction leakage is attributed to a very smooth interface.

Growth of GaN film on 150mm Si (111) using multilayer AlN∕AlGaN buffer by metal-organic vapor phase epitaxy method

High quality GaN film was successfully grown on 150mm Si (111) substrate by metal-organic vapor phase epitaxy method using AlN multilayer combined with graded AlGaN layer as buffer. The buffer layer structure, film quality, and film thickness are critical for the growth of the crack-free GaN film on Si (111) substrate. Using multilayer AlN films grown at different temperatures combined with graded Al1−xGaxN film as the buffer, the tensile stress on the buffer layer was reduced and the compressive stress on the GaN film was increased. As a result, high quality 0.5μm crack-free GaN epitaxial layer was successfully grown on 6in. Si substrate.

High quality Ge thin film grown by ultrahigh vacuum chemical vapor deposition on GaAs substrate

High-quality epitaxial Ge films were grown on GaAs substrates by ultrahigh vacuum chemical vapor deposition. High crystallinity and smooth surface were observed for these films by x-ray diffraction, transmission electron microscopy, and atomic force microscopy. Direct band gap emission (1550 nm) from this structure was detected by photoluminescence. Valence band offset of 0.16 eV at the Ge/GaAs interface was measured by x-ray photoelectron spectroscopy. N-type arsenic self-doping of 1018/cm−3 in the grown Ge layers was determined using electrochemical capacitance voltage measurement. This structure can be used to fabricate p-channel metal-oxide-semiconductor field-effect transistor for the integration of Ge p-channel device with GaAs n-channel electronic device.

Strained silicon thin-film transistors fabricated on glass

Strained-Si thin-film transistors were fabricated on glass substrate by direct transfer of a 35nm strained Si film onto glass. The strained Si films were originally grown on a relaxed SiGe layer on Si substrate. The tensile strain for the strained Si on glass (SSOG) was found to be 0.80%±0.02%. The effective electron mobility of the fabricated NMOS TFTs is 820cm2∕Vs. These devices show low interface charge densities at the bonding interface and at the gate oxide interface, as confirmed by the low subthreshold swing of 77mV∕dec for the 0.5μm SSOG device.

Fabrication and characterization of a Pb5Ge3O11 one-transistor-memory device

A Pb5Ge3O11 metal–ferroelectric–metal–oxide–silicon memory transistor has been fabricated. The device showed a memory window of about 2 V. The memory window was almost saturated at the operation voltage of 2 V. The “off” state drain current (ID) at VD of 0.1 V and VG of 0.5 V is about 1×10−8 A. The “on” state drain current (ID) at VD of 0.1 V and VG of 0.5 V is about 1×10−6 A, which is 100 times high than that of off state.

Effect of temperature on etch rate of iridium and platinum in CF4/O2

Iridium and platinum films were etched in the CF4/O2 plasma in an electron cyclotron resonance etch reactor. Wafers were placed on a heated chuck during etching, with the temperature maintained in the range of 70–250 °C before etching. A rf power was applied to the wafer chuck to generate a self-bias potential. At temperature below 100 °C, the iridium etch rate was low value. The iridium etch rate increased with temperature, and reached about 1500 A/min above 200 °C. Platinum also showed a low etch rate value below 150 °C, increasing to about 1500 A/min at 250 °C. The increase of etch rate at higher temperature was attributed to the formation of volatile compounds, IrF6 or PtF6.

Fabrication and Characterization of Sub-Micron Metal-Ferroelectric-Insulator-Semiconductor Field Effect Transistors with Pt/Pb5Ge3O11/ZrO2/Si Structure

The first metal-ferroelectric-insulator-semiconductor field effect transistors (MFIS FETs) using Pt/Pb5Ge3O11/ZrO2/Si structure has been successfully fabricated. The integration process is simple and reliable, and it is fully compatible with conventional complementary metal oxide semiconductor (CMOS) process. The smallest working device obtained is 0.3 µm×0.5 µm (L×W). The memory window is as large as 3 V and it is not dependent on device size. The endurance of the device is at least 108 cycles without degradation. The memory window decreased to 80% and 75% of initial values after 104 seconds retention tests at room temperature and 100°C respectively.

Selective deposition of TiSi2 on ultra-thin silicon-on-insulator (SOI) wafers

Chemical vapor deposition of TiSi 2 film on silicon film as thin as 97 A was demonstrated using a gas mixture of TiCl 4 , SiH 4 , SiH 2 Cl 2 , and H 2 . Selective deposition was observed on 97-180 A evaporated Si film and on SOI films with 220-450 A Si. On SOI film, transition of silicide to low resistance phase occurred at 26-28 s of deposition, as indicated by the resistance change. Silicide film was 650-700 A after a 35-s deposition. The Auger depth profile showed uniform film composition. Silicide film was also selectively deposited on polysilicon lines formed on SOI wafer. Transition to low resistance phase occurred also at 26-28 s in both 0.5 and 5 μm polysilicon lines. Silicide films formed on SOI structure were stable at 850°C. Films formed on polysilicon lines showed resistance increase when the deposition time was shorter. Phosphorus and BF2 implantation caused resistance increase in CVD silicide films. A subsequent RTA anneal restored the resistance to a value lower than 5 Ω/sq.

Improved linearity and reliability in GaN metal–oxide–semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.