Ching-Hsiang Hsu

A new 'shift and ratio' method for MOSFET channel-length extraction

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K.<<ETX>>

Optimized silicon-rich oxide (SRO) deposition process for 5 V only flash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO/sub 2/ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO/sub 2/ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm/sup 2/ at J=0.1 A/cm/sup 2/. The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices.<<ETX>>

Hot-electron-induced instability in 0.5- mu m p-channel MOSFETs patterned using synchrotron X-ray lithography

Radiation damage caused by X-ray includes positive oxide charge, neutral traps, and interface states. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron-induced instability in p-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. However, the degradation in n-channel MOSFETs due to channel-hot carriers is not significantly increased by X-ray lithography since n-channel MOSFETs are susceptible to interface state generation by hot carriers but are relatively insensitive to the degradation due to electron trapping. The results suggest that p-channel MOSFETs in addition to n-channel MOSFETs need to be carefully examined for hot carrier-induced instability in CMOS VLSI circuits patterned using X-ray lithography and/or when the radiation damage is incurred in the back-end-of-the-line processing.<<ETX>>

Saturation transconductance of deep-submicron-channel MOSFETs

Abstract A new method is described for extracting electron and hole saturation velocities from saturation currents of deep-submicron-channel N - and P MOSFETs at room and low temperatures. The extracted results are (7 ± 0.5) × 10 6 cm / s at 300 K and (8 ± 0.5) × 10 6 cm / s at 77 K for electrons; and (7 ± 1) × 10 6 cm / s at both 300 and 77 K for holes. These numbers are used in an analytical model to calculate the MOSFET saturation transconductance as a function of channel length. Excellent agreement is obtained between the experimentally measured saturation transconductance at 300 and 77 K and the model calculations over a wide range of channel length from 10 to 0.15 μm. This also sets up a procedure for identifying the onset of velocity overshoot, which is reflected in the 77 K N MOSFET data below 0.25 μm.

Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide

Very-high-transconductance 0.1 mu m surface-channel pMOSFET devices are fabricated with p/sup +/-poly gate on 35 AA-thick gate oxide. A 600 AA-deep p/sup +/ source-drain extension is used with self-aligned TiSi/sub 2/ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices.<<ETX>>

Radiation damage and its effect on hot-carrier induced instability of 0.5 mm CMOS devices patterned using synchrotron X-ray lithography

The device characteristics and the radiation damgae ofn-channel andp-channel MOSFETs patterned using synchrotron x-ray lithography are examined. The effect of radiation damage caused by x-ray lithography on the device reliability during hot electron injection is investigated. In addition to neutral traps, large amounts of positive oxide charge and interface states, particularly acceptor-like interface states, which cause degradation of MOSFET characteristics are found to be created by x-ray irradiation during the lithography process. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron induced instability inp-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. The effect of radiation damage on hot electron induced instability is found to be more severe inn+-poly buried-channelp-MOSFETs than inp+-poly surface-channel p-MOSFETs. However, the degradation inn-channel MOSFETs due to channel hot carriers is not significantly increased by x-ray lithography. These results suggest that the major degradation mechanism due to hot-carrier inp-channel MOSFETs is electron trapping and inn-channel MOSFETs is interface state generation. It also suggests thatp-channel MOSFETs, in addition ton-channel MOSFETs, needs to be carefully examined in terms of hot carrier induced instability in CMOS VLSI circuits patterned using x-ray lithography.

Effect of hydrogen annealing on hot-carrier instability of X-ray irradiated CMOS devices

In the very large scale integration (VLSI) technology, the need for high density and high performance integrated circuit (IC) chip demands advanced processing techniques that often result in the generation of high energy particles and photons. Frequently, the radiation damage are introduced by these energetic particles and photons during device processing. The radiation damage created by x-ray irradiation, which can often occur during metal sputtering process, has been shown to potentially enhance hot-carrier instability if the neutral traps which act as electron or hole traps in the silicon dioxide is not annealed out. In this paper, we investigate the effects of annealing using different hydrogen contents and temperatures on the device characteristics and hot carrier instability of 0.5 μm CMOS devices after 1500 mJ/cm2 synchrotron x-ray irradiation. Three different annealing conditions were employed; 400° C H2, 450° C H2, and 400° C H2 + N2. It is found that for all three different hydrogen anneals the normal characteristics of irradiated CMOS devices can be effectively recovered. The hot-carrier instability of bothp- andn-channel MOSFETs are significantly enhanced after x-ray irradiation due to the creation of neutral traps and positively charged oxide traps. After high H2 (100%) concentration anneals at 450° C, the hot-carrier instability in irradiatedn-channel devices is greatly reduced and comparable to the non-irradiated devices. Although the hot-carrier instability inp-channel devices is also significantly reduced after annealing, the threshold voltage shifts are still enhanced as compared to the devices without exposure to x-ray irradiation during maximum gate current stress. For those non-irradiated, but hydrogen-annealedp-channel devices, the hot-carrier instability was observed to be worse than the non-irradiated device without hydrogen annealing.

Hot-carrier induced instability of 0.5 mu m CMOS devices patterned using synchrotron X-ray lithography

The device characteristics and the radiation damage of n-channel and p-channel MOSFETs patterned using synchrotron X-ray lithography are examined. The effect of radiation damage caused by X-ray lithography on the device reliability during hot electron injection is investigated. Large amounts of positive oxide charge, neutral traps, and acceptor-like interface states are created by X-ray irradiation during the lithography process. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutron traps, is not completely annealed out. The hot-electron-induced instability in p-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. The effect of radiation on hot-electron-induced instability is found to be more severe in n/sup +/-poly buried-channel n-MOSFETs than in p/sup +/-poly surface-channel p-MOSFETs. However, the degradation in n-channel MOSFETs due to channel hot carriers is not significantly increased by X-ray lithography since the n-channel MOSFETs hot-carrier-induced degradation is dominated by interface state generation instead of electron trapping. These results suggest that p-channel MOSFETs, in addition to n-channel MOSFETs, need to be carefully examined in terms of hot-carrier-induced instability in CMOS VLSI circuits patterned using X-ray lithography. >