Jeremiah E. Golston

Single-chip H.324 videoconferencing

The C82 multimedia-processing DSP helps vendors respond to cost-sensitive consumer and PC markets. As shown here, it implements H.324 videoconferencing over analog phone lines.

Real-time MPEG video codec on a single-chip multiprocessor

We present a software implementation of a real-time MPEG video codec on the MediaStation 5000 multimedia system. Unlike other compression systems whose sole function is the encoding or decoding of video data, the MediaStation 5000 is capable of performing various real-time operations involving a wide range of multimedia data, including image, graphics, video, and even audio. This programmability is provided by Texas Instruments TMS320C80, better known as Multimedia Video Processor (MVP), which is a single-chip multiprocessing device with highly parallel internal architecture. The MVP integrates a RISC processor, four DSP-like processors, an intelligent DMA controller, video controllers, and a large amount of SRAMs onto a single chip. Since the MVP contains such a high degree of parallel features, developing the MPEG software and mapping it to the MVP requires a thorough study of the algorithms and a good understanding of the processor architecture. By exploiting the advanced features of the MVP, the MediaStation 5000 can achieve the MPEG compression and decompression of video sequences in real time.

DM642 digital media processor

This paper describes the new DM642 Digital Media Processor designed to support a broad range of video over packet applications. The DM642 includes the C64x VLIW DSP core optimized for video processing and flexible peripheral interfaces including three 20-bit video ports, a multi-channel audio serial port (McASP), Ethernet MAC, and PCI. The DM642 supports the full range of mature and emerging video compression algorithms including MPEG-2, MPEG-4, H.261, H.263, H.264, Windows Media, Real Video, and On2 VP5.

Strategies for mapping algorithms to mediaprocessors for high performance

For multimedia applications, mediaprocessors can achieve performance comparable to that of ASICs while remaining programmable and multifunctional. But a detailed understanding of the underlying architecture and algorithms is essential for developing efficient code. The authors present general strategies for mapping algorithms to mediaprocessors and discuss trends in mediaprocessing.

Optimized video decoder architecture for TMS320C64x DSP generation

The TMS320C64x DSP is a generation of high-speed DSPs with a rich instruction set and an efficient memory system for multimedia processing. Digital video decoding is one of the key applications in multimedia processing. It is a computationally intensive application, which requires high bandwidth to external memory and an efficient DMA engine. Reference models for video decoders typically follow a simple data flow that operates sequentially on one macroblock (MB) at a time. This structure leads to inefficiencies in real-time implementations including less than optimal utilization of program caches and DMA bandwidth. These issues become more significant with high-performance devices like the C64x DSP because the CPU efficiency and high-clock rate allow the core processing to occur much faster than on other processors. At the same time, the bandwidth to external memory has not increased at the same rate as the processing performance. This can lead the performance bottleneck to be I/O bandwidth instead of processing unless the system data flow is carefully designed. This paper describes an optimized flow for MPEG-2 decoding, which processes multiple blocks at a time to obtain optimum cache performance and DMA bandwidth efficiency. With this approach, system overhead is reduced from as high as 100% for worst-case B frames with the conventional flow to less than 20%.

C64x VelociTI.2 extensions support media-rich broadband infrastructure and image analysis systems

This paper describes the new C64x DSP core including instruction set extensions that enhance performance for image and video processing. Key features include packed data processing and special instructions to accelerate algorithms such as motion estimation. Devices based on the C64x will be ideally suited for key target applications including video infrastructure and image analysis.

Implementing a videoconferencing system based on a single-chip signal and image processor

This article describes an implementation of a flexible videoconferencing system, the Sony Mini‐1000, which is based on the Texas Instruments TMS320C80, a multiprocessor DSP, with software from IAT, Texas Instruments, and Sony. The H.320 videoconferencing standard used in the Mini‐1000 is described with emphasis on the H.261 video compression standard. We have heavily used many features of the TMS320C80 including the parallel processors optimized for imaging applications and the transfer controller, which is a powerful memory access engine. Mapping the H.320 standard on the Mini‐1000 system, particularly on the TMS320C80, is described in detail.

ARCHITECTURES AND VISUAL-PROCESSING APPLICATIONS OF MULTIMEDIA DSPS

Programmable digital signal processors (DSPs) are playing an increasingly important role in visual‐processing applications such as three‐dimensional graphics, image processing, and digital video. DSP architecture improvements, tuned to the data flow and algorithmic requirements of visual processing, are driving the proliferation of DSP use in these application areas. DSP software architectures are also undergoing significant changes to address the new challenges and opportunities created by the use of DSPs in these applications. This article provides an overview of the architecture and software developments in DSPs to meet the demanding needs of visual‐processing applications.