Karl M. Guttag

A single-chip multiprocessor for multimedia: the MVP

The multimedia video processor (MVP) architecture, which incorporates a variety of parallel processing techniques to deliver very high performance to a wide range of imaging and graphics applications, is described. The MVP combines, on a single semiconductor chip, multiple fully programmable processors with multiple data streams connected to shared RAMs through a crossbar network. Each of the independent processors can execute many operations in parallel every cycle. The architecture is scalable and supports different numbers of processors to meet the cost and performance requirements of different markets. MVPs target environment and the development of MVP are outlined.<<ETX>>

Video Display Processor

The Video Display Processor (VDP)*, a single chip video display system, is presented in this paper. The VDP provides high resolution color pattern graphics in combination with object oriented graphics, for display on an ordinary television receiver or simple monitor.

The TMS34010: an embedded microprocessor

The authors discuss the TMS34010, a high-performance 32-bit microprocessor with special instructions and hardware for handling the bit-field data and address manipulations often associated with computer graphics. They give a history of embedded microprocessors and examine the wide range of processors and applications covered by that term. They provide an overview of the internal architecture of the TMS34010 and discuss the choice of feature set in its design. Although it is aimed at graphics systems, the processors large address reach, bit-field processing, and DRAM (dynamic random-access memory) interface make it suitable for many other embedded processing applications.<<ETX>>

The Texas Instruments 34010 Graphics System Processor

The 34010 Graphics System Processor is a 32-bit graphics microprocessor capable of executing high-level languages. It combines a full general-purpose instruction set with a powerful set of graphics instructions that includes arithmetic as well as Boolean pixbits (pixel block transfers). Because it is completely programmable, the 34010 can be used in many different graphics and nongraphics applications. it was designed to support a wide range of display resolutions and pixel sizes, as well as applications such as page (laser) printers, ink jet printers, data compression, and facsimile transmission. The 34010 includes such system features as an on-board instruction cache, full interrupt capability, wait and hold functions, and display timing control, as well as test and emulation support. Unique among todays microprocessors, the 34010 addresses all memory down to the bit level with variably sized fields rather than the common byte or word addressing. For example, the 34010 can push a 5-bit quantity onto a stack. This field-processing capability is an integral part of the basic architecture.

Requirements for a VLSI Graphics Processor

This article will discuss issues that must be considered in the design of a VLSI (very large scale integration) 32-bit microprocessor specialized for graphics applications. With a properly chosen architecture, a single-chip graphics processor should provide a cost-effective means for achieving high performance in color bit-mapped graphics displays for PCs and workstations. The goal in selecting an architecture is to reduce the components required for a medium-to high-resolution display so they fit easily on a single, small, printed-circuit card. At the same time the processing speed must result in screen updates that occur without perceptible delay. These improvements should enable bit-mapped graphics displays to replace the text-only displays that have seen wide-spread use in cost-sensitive applications.

Compressing control ROM for VLSI microprogrammed microprocessors

By taking advantage of information redundancy and MOS structures, control ROMs for microprogrammed microprocessors can be considerably reduced. The Compressed Control ROM (CCROM) method for reducing control ROMs is described in terms of a simple example that compares the fully horizontal (unencoded) approach, the normal partially encoded approach, and the CCROM approach. Due to using CCROM, the effective cost of control ROM is considerably reduced, and this in turn can have a significant effect on the design approach by making it more cost effective to implement control signals directly from the control ROM rather than from random logic decodes.

TMS320C8x family architecture and future roadmap

The TMS320C8x family of Digital Signal Processors (DSP) incorporate multiple, high performance, fully programmable, processors onto a single CMOS die. The 320C80 has four 16/32-bit integer DSP CPUs, a 32-bit Floating Points RISC processor, 50 K bytes of SRAM, and a crossbar bus that can support over 4 Gigabytes of bandwidth. The 320C82 includes two of the integer DSPs, the RISC processor, 44 K bytes of SRAM, and a crossbar bus that can sustain over 2.6 Gigabytes of bandwidth per second. The C8x devices have special features that support general signal processing, telecommunication processing, and image processing. In addition to integrating multiple processors, the architecture includes on-chip Data RAM and instruction caches, as well as a very intelligent DMA controller, that support very high performance applications using lower cost off-chip memory. This paper concludes with a brief discussion of some of the future directions for this family of processors.

Computer graphics technology (panel session)

The extremely rapid growth of computer graphics is due, in large measure, to the application of leading-edge technology devices. Initially, these devices were not inspired by graphics applications. However, the market has become so large that display oriented semi-conductor devices are becoming specialty product lines. In turn these devices are leading to different display hardware architectures which will profoundly influence emerging capabilities in computer graphics. The future will be shaped as much by these technical innovations as by the economic trends they engender. The panel will examine the forces behind these technological changes and estimate their influence on directions for the computer graphics industry.

A 16b microprocessor with 152b wide microcontrol word

A data reduction method-compressed control ROM, yielding a 4 to 1 bit reduction, affording a 152b control word, will be described. The horizontal control produces better throughput by allowing simultaneous micro operations.