Jérémie Detrey

Table-based polynomials for fast hardware function evaluation

Many general table-based methods for the evaluation in hardware of elementary functions have been published. The bipartite and multipartite methods implement a first-order approximation of the function using only table lookups and additions. Recently, a single multiplier second order method of similar inspiration has also been published. This paper extends such methods to approximations of arbitrary order, using adders, small multipliers, and very small ad hoc powering units. We obtain implementations that are both smaller and faster than previously published approaches. This paper also deals with the FPGA implementation of such methods. Previous work have consistently shown that increasing the approximation degree lead to not only smaller but also faster designs, as the reduction of the table size meant a reduction of its lookup time, which compensated for the addition and multiplication time. The experiments in this paper suggest that this still holds when going from order 2 to order 3, but no longer when using higher order approximations, where a tradeoff appears.

Parameterized floating-point logarithm and exponential functions for FPGAs

As FPGAs are increasingly being used for floating-point computing, the feasibility of a library of floating-point elementary functions for FPGAs is discussed. An initial implementation of such a library contains parameterized operators for the logarithm and exponential functions. In single precision, those operators use a small fraction of the FPGAs resources, have a smaller latency than their software equivalent on a high-end processor, and provide about ten times the throughput in pipelined version. Previous work had shown that FPGAs could use massive parallelism to balance the poor performance of their basic floating-point operators compared to the equivalent in processors. As this work shows, when evaluating an elementary function, the flexibility of FPGAs provides much better performance than the processor without even resorting to parallelism. The presented library is freely available from http://www.ens-lyon.fr/LIP/Arenaire/.

Algorithms and Arithmetic Operators for Computing the ηT Pairing in Characteristic Three

Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. With software implementations being rather slow, the study of hardware architectures became an active research area. In this paper, we discuss several algorithms to compute the etaT pairing in characteristic three and suggest further improvements. These algorithms involve addition, multiplication, cubing, inversion, and sometimes cube root extraction over F3m. We propose a hardware accelerator based on a unified arithmetic operator able to perform the operations required by a given algorithm. We describe the implementation of a compact coprocessor for the field F397 given by F3[x]/(x97+x12+2), which compares favorably with other solutions described in the open literature.

A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic

For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at http://www.ens-lyon.fr/LIP/Arenaire/.

Arithmetic Operators for Pairing-Based Cryptography

Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. Software implementations being rather slow, the study of hardware architectures became an active research area. In this paper, we first study an accelerator for the i¾? T pairing over

A VHDL library of LNS operators

\mathbb{F}_3[x]/(x^{97}+x^{12}+2)

A parameterizable floating-point logarithm operator for FPGAs

. Our architecture is based on a unified arithmetic operator which performs addition, multiplication, and cubing over

Second Order Function Approximation Using a Single Multiplication on FPGAs

\mathbb{F}_{3^{97}}

A parameterized floating-point exponential function for FPGAs

. This design methodology allows us to design a compact coprocessor (1888 slices on a Virtex-II Pro 4 FPGA) which compares favorably with other solutions described in the open literature. We then describe ways to extend our approach to any characteristic and any extension field.

Floating-Point Trigonometric Functions for FPGAs

Logarithmic number system (LNS) have been shown to be a competitive replacement of floating-point (FP) arithmetic, for precisions up to 32 bits. This paper presents a library of LNS operators aimed at smaller precisions typical of DSP applications. The novelty of our approach is the use of multipartite table compression in the addition and subtraction operators. The paper compares this approach to other published implementations, and to similar FP operators. The operators have been developed and tested on FPGAs, but they are written in fairly standard VHDL. They are available for download from www.ens-lyon.fr/LIP/Arenaire.