Jeremy D. Dunworth

Direct conversion dual-band SiGe BiCMOS transmitter and receive PLL IC for CDMA/WCDMA/AMPS/GPS applications

A direct conversion 0.4/spl mu/m SiGe BiCMOS transmitter and receiver PLL consists of two transmitters, two PLLs, and an integrated VCO for cellular, PCS/IMT and GPS applications. The chip consumes 71mA at 2.7V with -55dBc ACPR at 885kHz offset and -134dBm/Hz noise at 45MHz offset for cellular, and 79mA, -56dBc ACPR at 1.25MHz offset, and -132dBm/Hz noise at 80MHz offset for PCS.

20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOS

Rapidly growing demand for broadband-cellular-data traffic is driving fifth-generation (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated using practical antenna arrays at 28GHz [1], and the FCC recently issued a notice of inquiry into the provision of mobile services above 24GHz. Battery life and thermal limitations make power efficiency critical in the envisioned user-equipment (UE) phased-array transceivers, particularly for power amplifiers (PAs), which operate at 8-to-10dB power back-off (PBO) to transmit broadband, high-peak-to-average power-ratio (PAPR) signals with high fidelity. Higher yields and lower costs for integrated phased arrays make CMOS the preferred choice over other more-power-efficient technologies, e.g. GaAs. Furthermore, calibrating an integrated array of PAs, e.g. by using digital pre-distortion, is prohibitively complex for high-volume manufacturing. Thus, maximizing PAE of inherently linear CMOS PA circuits at PBO is a major challenge for future 5G UE radios.

A Quadrature Switched Capacitor Power Amplifier

This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65 nm CMOS. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array. The I/Q signals are digitally weighted and combined in the charge domain. Quadrature summation results in a 3 dB signal loss; Hence the Q-SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. Unlike polar/EER counterparts, the Q-SCPA requires no wideband phase modulator or delay matching circuitry. The Q-SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%. It is measured with a 10 MHz, 64 QAM LTE signal, and achieves an ACLR of <;-30 dBc, with an EVM <; 4%-rms.

A quadrature switched capacitor power amplifier in 65nm CMOS

This paper presents a quadrature switched-capacitor power amplifier (SCPA) that achieves similar output power and efficiency as polar/EER based digital PAs. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array in the charge domain. The SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. This counteracts losses associated with the signal combination. Unlike polar/EER counterparts, the quadrature SCPA requires no wideband phase modulator or delay matching circuitry. The SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%.

2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS

To meet rising demand, broadband-cellular-data providers are racing to deploy fifth generation (5G) mm-wave technology, e.g., rollout of some 28GHz-band services is intended in 2017 in the USA with ∼5/1Gb/s downlink/uplink targets. Even with 64-QAM signaling, this translates to an RF bandwidth (RFBW) as large as ∼800MHz. With ∼100m cells and a dense network of 5G access points (APs), potential manufacturing volumes make low-cost CMOS technology attractive for both user equipment (UE) and AP devices. However, the poor Pout and linearity of CMOS power amplifiers (PAs) are a bottleneck, as ∼10dB back-off is typical for meeting error-vector-magnitude (EVM) specifications. This limits communication range and PA power added efficiency (PAE), with wider RFBWs accentuating these issues further. On the other hand, sufficient element counts in the envisaged 5G phased-array modules can overcome path loss despite low Pout per PA, e.g., by combining RFICs in an AP. CMOS PAs with wideband linearity/PAE can therefore enable economical UE/AP devices to deliver 5G data-rates.

Analysis of spectral spreading in a phase-modulated system for 1.75-GHz GSM RF transmitter design

An efficient and accurate analysis method to calculate the spectral spreading of a phase-modulated signal is presented. It accounts for two major non-idealities in a phase modulated system; (1) the phase error caused by circuit nonlinearity, (2) the additive spreading caused by LO spurious operation. The proposed method requires only a single-tone intermodulation simulation to fully characterize the spectral spreading in a phase-modulated system. Its accuracy is verified by comparing with the measurement results of a 1.75 GHz GSM RF transmitter.

A transformer combined quadrature switched capacitor power amplifier in 65nm CMOS

This paper presents a transformer combined, quadrature switched-capacitor power amplifier (Q-SCPA) that amplifies in-phase (I) and quadrature (Q) signals separately and combines them in a power-combining transformer. The unit SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. This counteracts losses associated with the signal combination. Unlike polar/EER counterparts, the Q-SCPA requires no wideband phase modulator or delay matching circuitry. The Q-SCPA delivers a peak (average) output power of 26 (18.5) dBm with a peak (average) PAE of 22% (18%) for a 20 MHz, 64 QAM OFDM signal with a simulated EVM of 4 % in the S-band.