Jerry J. Cupal

Redundant logarithmic arithmetic

A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic. >

Redundant logarithmic number systems

A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times.<<ETX>>

Initializing RAM-based logarithmic processors

A logarithmic processor is proposed that uses external RAM for holding the table required for logarithmic subtraction. The proposed processor requires that the RAM be initialized before any computations occur. We give an algorithm to initialize the RAM using the limited arithmetic unit of the processor. The algorithm is ten times faster than a bit by bit computation of the logarithm and antilogarithm. Bounds are developed for comparing the error of this algorithm against the error of earlier algorithms. Simulation results show that this algorithm avoids catastrophic cancellation, and is as accurate as any previously known single precision algorith.

On the cost effectiveness of logarithmic arithmetic for backpropagation training on SIMD processors

We show that backpropagation on a SIMD processor with logarithmic arithmetic uses less memory and may be up to 3.2 times more cost effective than on one with fixed point arithmetic when synthesized in the same technology.

Towards a formal model of hardware synthesized from Verilog

Formal verification offers a way to prevent costly design errors that are impractical to detect with simulation alone. Successful formal verification of hardware requires using automated theorem provers. Optimal synthesis requires providing high level (behavioral) Verilog to commercial synthesis tools, such as PLDesigner and Synopsys. The paper presents a novel approach, known as the volley technique, that allows a design to be coded in an analogous way both in Verilog HDL and in the LISP like syntax of the Boyer Moore theorem (R.S. Boyer and J.S. Moore, 1988). To illustrate the technique, a simple machine that computes Fibbonaci numbers is designed in Verilog and fabricated as an AMD MACH 210 CPLD.

A low-cost microcomputer based direct load control scheme for small electric utilities

Abstract A low-cost microprocessor based direct load control scheme is described. The scheme is particularly suitable for small- to medium-sized public utilities which do not possess large financial resources to implement a large-scale SCADA based load management system. The system is designed around the 8-bit 68HC11 microcontroller manufactured by Motorola. The hardware consists of two basic systems: the transmitter and the receiver. The transmitter consists of a PC, and HC11 Evaluation Board and a radio transmitter. The receiver consists of the radio receiver and an HC11 running in single-chip mode. The system uses an addressing scheme to control up to four loads at each of 4095 different receiver sites. It uses redundant data transmission to ensure error-free operation.

A purely behavioral data structure for accurate high level timing simulation of synchronous designs

It is difficult to develop pure behavioral Verilog models of synchronous digital systems (such as a CISC microprocessor) that produce accurate timing information using only the built-in reg declaration and blocking assignment statements. The authors present a novel behavioral module definition that can be instantiated instead of a reg to abstractly model synchronous register transfers with blocking assignment statements. The technique is easy to use because of Verilogs hierarchical naming and because the module automatically deals with the clock. Although simple register transfers could be modeled with non-blocking assignment, this technique has the advantage that it can be extended easily to deal with arbitrary depth pipelines. To introduce the technique, the authors examine the modeling of several instructions from the Motorola 68HC11 in both a multicycle implementation that matches the Motorola documentation and in a faster pipelined implementation.<<ETX>>