Jerzy W. Greblicki

Analysis of the Properties of the Harmony Search Algorithm Carried Out on the One Dimensional Binary Knapsack Problem

In the paper we carried out the analysis of the properties of the Harmony Search Algorithm (HSA) on a well known one-dimensional binary knapsack problem. Binary knapsack problems are among the most widely studied problems in discrete optimization. Since the optimization versions of these problems are nP-hard, practical solution techniques do not ask for optimality, but are heuristics that generate feasible, suboptimal solutions. In this paper we describe the 0-1 knapsack problem itself, the backgrounds of the HSA, Baldwin and Lamarck Effects and the numerical tests. The result of the tests performed is surprised a bit.

Cloud computing in educational applications methods of virtual desktops deployment

Task scheduling is one of the main parts of Cloud Computing (CC). We understand this process as mapping users tasks to appropriate resources to execute. Since we use virtual machines (VM) to hide physical resources form user the critical problem is how to schedule this machines (sub tasks) in given resources (ie. host machines). Tasks scheduling algorithms for CC systems are discussed in literature [2][4][5]. The most authors use mathematical model without consideration of many problems with desktop virtualization. In this paper we consider a new model for tasks scheduling of VM deployment for business and educational purposes. We also introduce genetic algorithm [1] for task scheduling in CC.

Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits

Several design methods of self-checking synchronous sequential circuits (SMs) have been proposed in the literature. In this paper, we present a new approach to designing totally self-checking (TSC) code-disjoint (CD) SMs protected against errors using unordered codes. It is assumed that D flip-flops are used as the memory elements and that the circuit should be TSC for all single stuck-at faults (except for the faults on the clock lines), and CD for all input unidirectional errors. The initial 2-level AND-OR equations (with all products shared) are checked for self-testing by verifying some algebraic conditions. All stuck-at-1 faults which cannot be detected during normal functioning are identified. Then, the circuit is modified to the AND-AND-OR circuit with generally higher fault coverage. The resulting circuit is minimized using the well known SIS CAD tools. The whole design process has been automated by using the newely developed software tools that accept the BLIF representation of a SM and are compatible with the SIS tools. Many benchmark SMs can now be implemented as TSC with 100% fault coverage.

State encoding and minimization methodology for self-checking sequential machines

State encoding methodology and minimization procedure for designing of reliable digital circuit - Totally Self Checking Sequential Machines is considered in this article. We limit considerations to Mealy sequential circuits with inputs, internal states and outputs encoded with any unordered code.

Automated Design of Totally Self-Checking Sequential Circuits

In this paper methods of designing of a class of highly reliable digital circuit - Totally Self Checking Sequential Machines are presented. The main problem in TSC sequential machines (TSC SM) designing is synthesis TSC functional excitation circuit. Formal condition of ST property for both AND-OR and AND-AND-OR structures are presented. The description of design methodology of TSC SM is presented. Owing to our methods we can design TSC circuits in a fully automatic way.

The cutting stock problem recent application in information technology

Cloud computing is a Web-based processing, that allow to share resources, software, and information over the Internet. Cloud computing helps enterprises and other institutions like schools, universities, etc. transform business and technology. Most cloud computing infrastructures consist of services delivered through common centers and built on servers.

CAD software for designing of Totally Self Checking Sequential Circuits

We present software for designing totally self checking sequential machines. We restrict our considerations to sequential circuits with inputs, internal states and outputs encoded with any unordered code. We propose theorems to verify self testing (ST) and code-disjoin (CD) properties. Circuits tested as not ST or/and CD are modified to obtain those properties. We also propose a method for internal states encoding which guarantees ST of self testing checker (STC) circuit for internal states code. Owing to our methods we can design TSC circuits in a fully automatic way

SmartCloud Orchestrator—the First Implementation for Education in the World at WrUT

SmartCloud Orchestrator provides a consistent, flexible, and automated way of integrating the cloud with customer data center policies, processes, and infrastructures across various IT domains, such as backup, monitoring, and security. It proposes the intuitive, graphical tool to define and implement business rules and IT policies. One can connect the aspects of different domains into a consistent orchestration of automated and manual tasks to achieve the business goals. SmartCloud Orchestrator is based on a common cloud platform that is shared across IBM’s Cloud offerings. This common cloud stack provides a common realization of the core technologies for comprehensive and efficient management of cloud systems. Last year, at the end of November, Wroclaw University of Technology, due to co-operation with IBM Corporation, put this tool into the motion for education purposes, between others.

Design of Totally Self-Checking Sequential Circuits

Methods of designing of Totally Self Checking Sequen- tial Machines are presented in this paper. The main problem in TSC sequential machines (TSC SM) designing is synthesis TSC functional excitation circuit. Formal condition of self testing (ST) property for AND-OR structures are given. New method of circuit minimization is presented and ST of minimized circuits is proofed. We also present a methodology of designing of TSC SM. Owing to our methods we can design TSC circuits in a fully automatic way.

Determination of the Optimal Routes for Autonomous Unmanned Aerial Vehicle Under Varying Wind with Using of the Traveling Salesman Problem Algorithm

The goal of this paper is to propose and test the algorithm for traveling salesman problem (TSP) for autonomous unmanned aerial vehicles. In this paper we consider the situation when the multicopter is flying under a variable wind and is intended to visit indicated points. We analyze the efficiency of the algorithm in case of limited flying time on a constant height.