Jesse Galloway

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.

Thermal Test Chip Design and Performance Considerations

Increasing device complexity, greater power densities, ever changing packages, and shorter time-to-market deadlines have combined to make thermal characterization efforts more frenzied than ever. A thermal test chip was designed to assist the thermal engineer in answering critical thermal packaging or material questions. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scaleable array size. This allows a single wafer to supply various array sizes to meet changing requirements. The key requirements for a thermal test chip are: (1) Maximum possible heating area relative to chip size (2) Uniform temperature profile across heating area (3) Low temperature coefficient for heating source (4) Temperature sensor in center of chip (5) Simple-to-use temperature sensor(s) (6) Multiple temperature sensors for a temperature profile across chip surface (7) Kelvin Connections (i.e., 4-wire connections) for improved measurement accuracy (8) Chip size that closely approximates the chip being simulated. This paper will describe a thermal test chip that meets these requirements in the simplest manner possible. Insight into future investigations will also be presented.

Impact of heatsink attach loading on FCBGA package thermal performance

Flip-Chip Ball Grid Array (FCBGA) packages are prevalent in wide range of electronics applications including gaming consoles, mobile gadgets, telecommunications etc. The microelectronics industry is actively shifting towards smaller node sizes (32 nm, 28 nm etc.) and integrating multiple functionalities onto the die. This in turn increases the die power levels and more importantly drastically increases the die heat-flux densities. External heatsinks are typically needed in order to support high thermal power dissipation. The focus of this paper is to understand and quantify the impact of heatsink tilt on board-level thermal performance. her This in turn impacts the overall thermal performance as higher TIM-II bond line thickness results in greater thermal resistance. For high power applications (>;50W) wherein the desired system thermal resistances are very low (θja <; 1 C/W), controlling the TIM-II thermal resistance is critical to achieve an overall low system thermal resistance. Experimental measurements were performed using a high power FCBGA thermal test vehicle (TTV). The scope of this study includes performing thermal measurements to -level thermal understand the impact of the following on board performance: 1. Package type: Bare Die FCBGA, Molded FCBGA & Lidded FCBGA 2. Impact of uneven heat-sink loading A novel method for characterizing TIM-II thickness variation is presented in this work. Upon characterizing the TIM-II BLT thickness variation, experimental measurements were performed to quantify the impact on the board-level thermal performance. Finally, merit analysis of the various package types in achieving low overall package thermal resistance will be presented.

TIM selection methodology for high power flip chip packages

Flip-chip packages are currently used for various applications such as desktop computers, servers, gaming, telecommunications, etc. Due to tremendous demand of die functionality, the power levels and more importantly the die heat-flux densities are drastically increasing, thus customers are constantly pushing packaging industries to lower thermal impedance of TIM for very high power flip chip packages. To achieve the target, TIM formulation focuses on filler type, size, loading, etc. Typically low modulus gel and grease type TIM are filled with Al2O3, Ag, Ga, Al, etc filler. Fillers are designed for high-performance, and high power application. The cross-linking properties of gel or grease type TIM should have enough strength so it can comfortably overcome squeeze or pump-out issue during highly accelerated package reliability tests. Package designers typically focus more on the thermal issues for TIM performance evaluation, characterization, and formulation, but there is not much study available [2–9] on TIM degradation in the packages and its actual thermal performance. Costly gel, grease, or solder polymer type materials have very good thermal properties, but during actual package reliability test sometimes they perform poorly due to excessive voids, pump-out, interface delamination, and other degradation issues [1]. This study started to meet more demanding thermal solutions by maintaining comprehensive TIM selection methodology with standard testing processes and materials to quantify future thermal load. While thermal performance is the primary target, mechanical vs thermal performance tradeoffs are investigated through extensive package reliability analysis for high power flip chip packages.

Extracting TIM properties with localized transient pulses

Thermal engineers require accurate package-level resistance estimates to design optimized cooling systems. Although Theta-JC is a commonly quoted metric to define the junction to case resistance, it does not accurately predict package performance for a range of heat sink and thermal interface material (TIM) conditions. To overcome this limitation, a steady-state and a transient test method is presented to extract the thermal resistance of the TIM. A high resistance adhesive, a low resistance gel and an Indium TIM are investigated. The transient method is shown to be approximately 20% more accurate compared to the steady-state method and also simplifies both the experimental testing and corresponding numerical simulations.

Accurate Theta jc measurement for high power packages

Measuring the case temperature is one of the most challenging measurements for determining the junction-to-case thermal resistance (Theta jc) in high power packages. This is especially true for low Theta jc measurement, in which high power is necessary to control accuracy. Inaccurate case temperature measurement would lead to an inaccurate Theta jc value. This study explores different methods for measuring case temperature and quantifies their impact on Theta jc. A new method of cold-plate protruded thermocouple is proposed and compared with commonly adopted method of lid embedded thermistor both experimentally and numerically. It is found correction is not negligible for low Theta jc measurement in both methods due to the temperature difference between the case surface and the thermal probe location. A standard test jig is also proposed to determine the correction for the cold-plate protruded thermocouple experimentally.

BLT control and its impact on FCBGA thermal performance

The performance of high power packages is limited in part by the interfacial resistance between the die and lid or heat sinks. The thermal resistance depends on the shape of mating surfaces, bondline thickness (BLT) of the thermal interface material (TIM), bulk thermal conductivity and contact resistance. This paper focuses on warpage modeling methods to predict the local variation of TIMs and its impact on thermal resistance as a function of assembly processes. Experimental data and simulations show that when packages are soldered to the motherboard, they tend to have less warpage than unmounted packages. A 17% reduction in thermal resistance was predicted for a bare die package once soldered to the mother board. Close agreement between warpage simulations and experimental measurements is observed.

Decoupled Package-On-Package thermal characterization

Thermal characterization of a Package-On-Package (PoP) presents a challenge due to the variation in stacking configurations. Currently available characterization methods as outlined in the JESD51 standard cannot predict die temperatures for packages with more than one die, let alone multiple stacked packages. A model is presented to predict die temperatures for PoP by combining individual resistor networks using a Delphi network modeling approach. Data from experimental tests were used to confirm the accuracy of a Finite element analysis (FEA) based conduction model for an assembled PoP under varying power combinations. Separate FEA models for top and bottom packages were used to extract resistance values for two different resistor networks. These network models were combined to predicted die temperatures with a difference less than 7% when compared to the FEA model of the PoP.

Implementing compact thermal models under non-symmetric trace routing conditions

Compact thermal models (CTMs) are used to reduce the size and time required to solve system thermal models while still maintaining a high level of simulation accuracy. Methods for developing and validating CTMs under symmetrical boundary conditions are well understood. However, they do no always accurately predict the thermal solution for nonsymmetrical boundary conditions arising from either developing flow and/or non-uniform trace routing conditions. Presented in this study is a detailed analysis of a super ball grid array (SBGA) and a carrier array ball grid array (CABGA) style packages. Also presented are two-resistor models, symmetric and non-symmetric compact models. Two-resistor models were shown to underestimate the thermal resistance while Delphi style compact models tend to overestimate the thermal resistances for the SBGA and CABGA packages considered in this study. A method of accounting for non-symmetrical printed circuit board (PCB) routing conditions is also presented.

Mechanical, thermal and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.