Jesus N. Calata

Low-Temperature Sintered Nanoscale Silver as a Novel Semiconductor Device-Metallized Substrate Interconnect Material

A nanoscale silver paste containing 30-nm silver particles that can be sintered at 280degC was made for interconnecting semiconductor devices. Sintering of the paste produced a microstructure containing micrometer-size porosity and a relative density of around 80%. Electrical and thermal conductivities of around 2.6times105 (Omegamiddotcm)-1 and 2.4W/K-cm, respectively, were obtained, which are much higher than those of the solder alloys that are currently used for die attachment and/or flip-chip interconnection of power semiconductor devices. The sintered porous silver had an apparent elastic modulus of about 9GPa, which is substantially lower than that of bulk silver, as well as most solder materials. The lower elastic modulus of the porous silver may be beneficial in achieving a more reliable joint between the device and substrate because of increased compliance that can better accommodate stress arising from thermal expansion mismatch

Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area

A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125°C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275°C with the sintered joints having the melting temperature of silver at 961°C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications.

({>}100~{\rm mm}^{2})

Screen/stencil-printable nanosilver pastes were processed and characterized for die-attaching SiC devices. The nanosilver pastes were made by mixing silver particles in diameter with an organic binder vehicle. For the die-attachment, the nanosilver pastes were printed onto silver-coated or gold-coated direct-bond-copper (DBC) substrates. After die-attaching the SiC devices, the assemblies were heated to 300 with a 40-min dwell time to develop bonding up to 40 MPa on the silver-coated substrates, which was comparable to that of the Pb37Sn63 solder die-attachment. Scanning acoustic microscopy (SAM) of the sintered silver die-attachment did not reveal any detectable voids, while scanning electron microscopy (SEM) showed the presence of uniformly distributed microscale pores. Because of the porous microstructure of the sintered silver and its low apparent elastic modulus, it could help relieve thermomechanical stresses in the die-attachment assembly. Finally, since silver die-attachment is almost pure in constituent (>99%), the die-attachment could enable packaging of wide bandgap semiconductors devices, such as SiC or GaN, for high-temperature operation.

Chips

Control of the low-temperature sintering of nanosilver particles was attained by dispersing and stabilizing nanosilver particles into a paste form using the selected organic binder systems. As demonstrated by scanning electron microscopy (SEM) and thermogravimetric analysis (TGA), with the existing binder systems, undesirable premature coalescence of nanosilver particles was prevented and the metastable structure was retained until the binder burned out at relatively higher temperatures. Enhanced densification was achieved upon the binder burnout because at the relatively higher temperatures the densification mechanisms, e.g., grain-boundary or lattice diffusion, become more dominant. We propose that the onset of sintering, extent of densification, and final grain size can be controlled by either the size of the initial nanosilver particles or the binder systems with different burnout characteristics.

Processing and Characterization of Nanosilver Pastes for Die-Attaching SiC Devices

Demands for increasing power density and levels of functional integration in switch-mode power converters require power electronics manufacturers to develop innovative packaging solutions for power semiconductor devices and modules. Three-dimensional (3-D) packaging techniques offer the potential of lower resistance, higher current handling capability, smaller volume, better thermal management capability, and high reliability. In this paper, we present the constructions and some electrical and thermomechanical analyses of four 3-D packaging approaches that have been developed within the Center for Power Electronics Systems-an NSF Engineering Research Center.

Control of nanosilver sintering attained through organic binder burnout

We present an interconnect technology based on low-temperature and pressureless sintering of a nanoscale metal paste to achieve high-performance and high-temperature packaging of semiconductor devices. The nanoscale metal paste, consisting of nanoparticles of silver mixed in an organic binder/solvent vehicle, can be sintered at temperatures close to 275degC. Measurements on electrical and thermal properties of the sintered die interconnect gave it at least five times better than the soldered or epoxied attachment. Die-shear tests of the sintered joints showed a bonding strength of about 25 MPa. The sintered joints exhibited excellent reliability in aging and temperature-cycling tests. Since silver melts at 961degC, the sintered interconnect can be used for wide band gap semiconductor devices (SiC or GaN), which are operable over 300degC where none of the existing solder alloys or epoxies can be used. In summary, the low- temperature sintering of nanoscale metal paste is shown to be a reliable, lead-free interconnect solution for high-temperature and high-performance packaging needs.

Three-dimensional packaging for power semiconductor devices and modules

Substrate reliability has, for a long time, been a concern for systems exposed to harsh environments. State-of-the-art direct bond copper (DBC) substrate is susceptible to large-temperature cycling range. Due to the coefficient of thermal expansion mismatch between copper and the base ceramic (e.g., Al2O3 and AlN), delamination of copper from the ceramic base plate caused by thermomechanical stresses is often observed. In this paper, effects of large-temperature cycling range on direct bond aluminum (DBA) substrate reliability were investigated as it could be a viable alternative to DBC. DBA substrates with different metallizations were thermally cycled between -55degC and 250degC. Unlike the DBC substrate, no delamination of aluminum from the aluminum-nitride ceramic base plate was observed in the DBA substrates. However, it was observed that surface roughness of metallization increased during the thermal cycling test. It is believed that, in the high-temperature regime, the significant amount of thermal stress and grain-scale deformation caused recrystallization and grain-boundary sliding to become very active in the aluminum layer, thus leading to the observed increase in surface roughness. The influence of metallization over the aluminum surface on the extent of surface roughness was also characterized.

Low-temperature and Pressureless Sintering Technology for High-performance and High-temperature Interconnection of Semiconductor Devices

Sintered nanosilver is a lead-free die-attach material that could substitute for solder alloys and conductive epoxies for packaging power semiconductor devices, especially for high-temperature applications. While the maximum use temperature of a solder is limited by its melting point, the sintered silver joint can be used above the processing temperature, thus enabling high-performance power devices based on SiC technology to operate at high temperature. It can be fired at temperatures below 300°C without requiring applied pressure to form a dense interconnection with thermal and electrical conductivities superior to those of common high-temperature solder alloys. Die-shear strengths between 25 and 35 MPa can be obtained which compares favourably to the shear strength of solder. Unlike solder, which tends to form large voids during reflow, the sintered silver has a low elastic modulus and a microstructure containing only randomly distributed micrometer-scale pores that eliminates hot spots in the joint.

Effects of Large-Temperature Cycling Range on Direct Bond Aluminum Substrate

Solder-bump (SB) and direct-solder (DS) interconnections offer the possibility of double-sided cooling for packaging power devices. In this paper, packages with SB and DS bonded power devices were fabricated to investigate their reliability and the effectiveness of double-sided cooling. Thermal and thermomechanical characteristics of both packages were analyzed via temperature cycling experiment and computer simulation by finite element modeling (FEM). Thermal analysis results show that double-sided cooling is more effective in the DS package and it has a significantly lower device operating temperature; however, if the same temperature range of cycling is imposed on both packages, the mismatched coefficients of thermal expansion (CTE) lead to larger thermally induced stresses at the silicon-solder interface in the DS package. From a combined thermal and thermomechanical point of view, the DS package is superior over the SB package because the former is expected to experience less temperature changes during operation than the latter one. Locations of maximum stresses in the FEM analysis are also consistent with the crack initiation positions observed in the temperature-cycled packages.

Sintered nanosilver paste for high-temperature power semiconductor device attachment

Die attach by low-temperature sintering of nanoparticles of silver is an emerging lead-free joining solution for electronic packaging because of the high thermal/electrical conductivity and high reliability of silver. For bonding small chips, the attachment can be achieved by a simple heating profile under atmospheric pressure. However, for bonding chips with an area , an external pressure of a few MPa is reported necessary at the sintering temperature of ~ 250 °C. This hot-pressing process in excess of 200 °C can add significant complexity and costs to manufacturing and maintenance. In this paper, we conduct a fractional factorial design of experiments aimed at lowering the temperature at which pressure is required for the die-attach process. In particular, we examine the feasibility of applying pressure only during the drying stage of the process when the temperature is still at 180 °C. The experiments help to identify the importance and interaction of various processing parameters, such as pressure, temperature, and time, on the bonding strength and microstructure of sintered nanosilver joints. In addition, the positive effect of pressure applied during drying on the bonding quality is observed. With the results, a simpler process, consisting of pressure drying at 180 °C under 3 MPa pressure, followed by sintering at 275 °C under atmospheric pressure, is found to produce attachments with die-shear strengths in excess of 30 MPa.