John G. Bai

Low-Temperature Sintered Nanoscale Silver as a Novel Semiconductor Device-Metallized Substrate Interconnect Material

A nanoscale silver paste containing 30-nm silver particles that can be sintered at 280degC was made for interconnecting semiconductor devices. Sintering of the paste produced a microstructure containing micrometer-size porosity and a relative density of around 80%. Electrical and thermal conductivities of around 2.6times105 (Omegamiddotcm)-1 and 2.4W/K-cm, respectively, were obtained, which are much higher than those of the solder alloys that are currently used for die attachment and/or flip-chip interconnection of power semiconductor devices. The sintered porous silver had an apparent elastic modulus of about 9GPa, which is substantially lower than that of bulk silver, as well as most solder materials. The lower elastic modulus of the porous silver may be beneficial in achieving a more reliable joint between the device and substrate because of increased compliance that can better accommodate stress arising from thermal expansion mismatch

Processing and Characterization of Nanosilver Pastes for Die-Attaching SiC Devices

Screen/stencil-printable nanosilver pastes were processed and characterized for die-attaching SiC devices. The nanosilver pastes were made by mixing silver particles in diameter with an organic binder vehicle. For the die-attachment, the nanosilver pastes were printed onto silver-coated or gold-coated direct-bond-copper (DBC) substrates. After die-attaching the SiC devices, the assemblies were heated to 300 with a 40-min dwell time to develop bonding up to 40 MPa on the silver-coated substrates, which was comparable to that of the Pb37Sn63 solder die-attachment. Scanning acoustic microscopy (SAM) of the sintered silver die-attachment did not reveal any detectable voids, while scanning electron microscopy (SEM) showed the presence of uniformly distributed microscale pores. Because of the porous microstructure of the sintered silver and its low apparent elastic modulus, it could help relieve thermomechanical stresses in the die-attachment assembly. Finally, since silver die-attachment is almost pure in constituent (>99%), the die-attachment could enable packaging of wide bandgap semiconductors devices, such as SiC or GaN, for high-temperature operation.

Three-dimensional packaging for power semiconductor devices and modules

Demands for increasing power density and levels of functional integration in switch-mode power converters require power electronics manufacturers to develop innovative packaging solutions for power semiconductor devices and modules. Three-dimensional (3-D) packaging techniques offer the potential of lower resistance, higher current handling capability, smaller volume, better thermal management capability, and high reliability. In this paper, we present the constructions and some electrical and thermomechanical analyses of four 3-D packaging approaches that have been developed within the Center for Power Electronics Systems-an NSF Engineering Research Center.

A lead-free, low-temperature sintering die-attach technique for high-performance and high-temperature packaging

For semiconductor devices to function in products, they need packaging to provide interconnection and protection. Die-attach materials, which join the devices to the rest of the system, play a vital role in ensuring the system performance and reliability. Today, lead-tin and lead-free solder alloys, and conductive epoxies are widely used for attaching the devices because they can be easily processed at a temperature below 300/spl deg/C. As the electronics industry continues to integrate more functions in smaller packages, the electrical, thermal, and mechanical properties of the existing die-attach materials do not meet the more demanding requirements for performance and reliability. In this talk, a die-attach technique based on sintering of silver pastes to interconnect devices are presented. Two strategies have been adopted to lower the sintering temperature down to 300/spl deg/C: one involves using quasi-hydrostatic pressure to increase the sintering driving force; while the other relies on nanoscale silver particles to densify the material without pressure. Experimental measurements on the sintered joints show significantly improved electrical, thermal, and mechanical properties over the soldered joints. This silver-sintering die-attach technique opens the possibility for interconnecting wide band gap semiconductor devices (SiC or GaN) that are operable over 350/spl deg/C where none of the existing solder alloys can be used.

Inkjet printable nanosilver suspensions for enhanced sintering quality in rapid manufacturing

Inkjet printable nanosilver suspensions were prepared by dispersing 30 nm silver particles into a water-based binder system to enhance the sintering quality in rapid manufacturing. During three-dimensional printing (3DP), the nanosilver suspensions were inkjet printed onto repetitively spread microsilver powder for selective joining. Since the nanosilver particles in the suspensions can be sintered at relatively low temperatures to bond the neighbouring microsilver powder, they were used to provide the continuous bonding strength of the manufacturing parts during the heat-up procedure of the sintering operation. Comparative study shows that the silver parts printed using the nanosilver suspension were significantly enhanced in sintering quality than those printed using the binder system, especially when the silver parts had thin or small features with high aspect ratios.

Comparative thermal and thermomechanical analyses of solder-bump and direct-solder bonded power device packages having double-sided cooling capability

Solder-bump (SB) and direct-solder (DS) interconnections offer the possibility of double-sided cooling for packaging power devices. In this paper, packages with SB and DS bonded power devices were fabricated to investigate their reliability and the effectiveness of double-sided cooling. Thermal and thermomechanical characteristics of both packages were analyzed via temperature cycling experiment and computer simulation by finite element modeling (FEM). Thermal analysis results show that double-sided cooling is more effective in the DS package and it has a significantly lower device operating temperature; however, if the same temperature range of cycling is imposed on both packages, the mismatched coefficients of thermal expansion (CTE) lead to larger thermally induced stresses at the silicon-solder interface in the DS package. From a combined thermal and thermomechanical point of view, the DS package is superior over the SB package because the former is expected to experience less temperature changes during operation than the latter one. Locations of maximum stresses in the FEM analysis are also consistent with the crack initiation positions observed in the temperature-cycled packages.

Thermomechanical reliability of low-temperature sintered silver die-attachment

In this paper, we present a thermomechanical reliability study on the low-temperature sintered silver die-attachment for packaging semiconductor devices. The die-attachment was formed by sintering nanoscale silver paste at 300degC for 40 minutes to develop full adhesion strength between silver-coated direct-bond-copper (DBC) or copper substrates and silver-metallized SiC devices. A strong bond was formed between the die and substrate with the die-shear strength reaching 40 MPa. Using a 50% drop in the die-shear strength as the failure criterion, accelerated temperature-cycling test between 50degC and 250degC showed that the sintered silver die-attachment on DBC substrates can survive beyond 4000 cycles, indicating high reliability at the temperature cycling range. Scanning electron microscopy (SEM) observations suggest that the die-attachment failure is due to ductile fracture in the silver attachment as micro-cavities were nucleated at grain boundaries during temperature cycling. Results obtained in this study demonstrate that the low-temperature sintered silver is a promising lead-free and reliable die-attach solution for semiconductor devices. Additionally, the silver die-attachment is a potential solution for high-temperature electronics packaging because its high-temperature reliability exhibited during the temperature cycling

Discussion on the Reliability Issues of Solder-Bump and Direct-Solder Bonded Power Device Packages Having Double-Sided Cooling Capability

Power device packages with solder-bump (SB) and direct-solder (DS) interconnections were fabricated and some of their thermomechanical reliability issues were discussed based on both thermal cycling experiment and finite element analysis (FEA). The SB interconnection shows superior reliability over the DS interconnection in the thermal cycling experiment because the mismatched coefficient of thermal expansion leads to smaller stresses at the SB interconnection under the same temperature changes. On the other hand, FEA results show that the DS package has significantly lower operating temperatures under the same double-sided cooling condition. After considering the operating temperature difference, the DS package was shown to be superior over the SB package in the power cycling analysis.

Determination of interfacial thermal resistivity by finite element modeling of the flash measurements

The flash technique is widely used to determine thermophysical properties of materials and it can be used to determine interfacial thermal resistivity in multilayer composites. However, the existing data analysis tool for calculating the interfacial thermal resistivity from the flash measurements can only deal with a simple bi-layer structure. Thermophysical properties of the middle layer material in a sandwiched structure would be overlooked during the calculation. The abstract mathematical calculation, complicated expressions, and tedious software coding limit the usefulness of the technique and prevent its application to more complex composite structures, such as those commonly seen in electronic packages. In this paper, we introduce the use of finite element modeling (FEM) for determining interfacial thermal resistivity from flash measurements of multilayer composite structures. The methodology was firstly applied to Cu/Sn-37Pb/Cu sandwiched specimens to determine the Cu/Sn-37Pb interfacial thermal resistivity. Making use of half temperature rise times obtained from the flash experiment, the sample structures were recreated in I-deas/spl trade/ and transient thermal FEM was performed for determining the Cu/Sn-37Pb interfacial thermal resistivity. Compared with the existing data analysis tool, the FEM method is more accurate for dealing with the multilayer structures because it takes into account thermophysical properties of the middle layer solder.

Shadow Edge Lithography for Wafer-Scale Nanofabrication

We propose shadow edge lithography (SEL) as a wafer-scale nanofabrication method. The shadow effect of “line-ofsight” in high-vacuum evaporation is analyzed theoretically to predict the geometric distributions of the fabricated nanoscale gaps. In the experiment, nanoscale gap patterns are created by the shadow of Al edges which are prepatterned using e-beam evaporation and the conventional ultraviolet lithography. Feasibility of the SEL is demonstrated by the fabrication of nanogaps having the width ranging from 15 to 100 nm on 4-inch Si wafers. Furthermore, by using the height differences in the prepatterned Al edges to compensate the geometric distributions of the shadow effect, it is demonstrated that the uniformity tolerance in the nanogap width can be ±1 nm or ±5% across the 4-inch Si wafers at a resolution down to 20 nm. The experimental results agree well with the theoretical prediction considering the virtual source during the e-beam evaporation. Upon the nanogap fabrication, arrays of nanochannels are obtained by reactive ion etching (RIE) using the evaporated Al layers as the etching mask. Our results show that that the evaporated Al layers can be used as the RIE mask to transfer the nanoscale patterns with a high yield and throughput. Thus, the SEL provides a robust method for wafer-scale fabrication especially for sub 50-nm structures.Copyright