Jewook Ha

Large-area formation of self-aligned crystalline domains of organic semiconductors on transistor channels using CONNECT

Significance Solution-processed organic electronics are expected to pave the way for low-cost large-area electronics with new and exciting applications. However, realizing solution-processed organic electronics requires densely packed transistors with patterned and precisely registered organic semiconductors (OSCs) within the transistor channel with uniform electrical properties over a large area, a task that remains a significant challenge. To address such a challenge, we have developed an innovative technique that generates self-patterned and self-registered OSC film with low variability in electrical properties over a large area. We have fabricated highest density of transistors with a yield of 99%, along with various logic circuits. This work significantly advances organic electronics field to enable large-scale circuit fabrication in a facile and economical manner. The electronic properties of solution-processable small-molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large-area electronic applications. However, practical applications of organic electronics require patterned and precisely registered OSC films within the transistor channel region with uniform electrical properties over a large area, a task that remains a significant challenge. Here, we present a technique termed “controlled OSC nucleation and extension for circuits” (CONNECT), which uses differential surface energy and solution shearing to simultaneously generate patterned and precisely registered OSC thin films within the channel region and with aligned crystalline domains, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half-adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication.

Transparent Large-Area MoS2 Phototransistors with Inkjet-Printed Components on Flexible Platforms

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) have gained considerable attention as an emerging semiconductor due to their promising atomically thin film characteristics with good field-effect mobility and a tunable band gap energy. However, their electronic applications have been generally realized with conventional inorganic electrodes and dielectrics implemented using conventional photolithography or transferring processes that are not compatible with large-area and flexible device applications. To facilitate the advantages of 2D TMDCs in practical applications, strategies for realizing flexible and transparent 2D electronics using low-temperature, large-area, and low-cost processes should be developed. Motivated by this challenge, we report fully printed transparent chemical vapor deposition (CVD)-synthesized monolayer molybdenum disulfide (MoS2) phototransistor arrays on flexible polymer substrates. All the electronic components, including dielectric and electrodes, were directly deposited with mechanically tolerable organic materials by inkjet-printing technology onto transferred monolayer MoS2, and their annealing temperature of <180 °C allows the direct fabrication on commercial flexible substrates without additional assisted-structures. By integrating the soft organic components with ultrathin MoS2, the fully printed MoS2 phototransistors exhibit excellent transparency and mechanically stable operation.

One-Step Interface Engineering for All-Inkjet-Printed, All-Organic Components in Transparent, Flexible Transistors and Inverters: Polymer Binding

We report a one-step interface engineering methodology which can be used on both polymer electrodes and gate dielectric for all-inkjet-printed, flexible, transparent organic thin-film transistors (OTFTs) and inverters. Dimethylchlorosilane-terminated polystyrene (PS) was introduced as a surface modifier to cured poly(4-vinylphenol) dielectric and poly(3,4-ethylenedioxythiophene):polystyrenesulfonate (PEDOT:PSS) electrodes without any pretreatment. On the untreated and PS interlayer-treated dielectric and electrode surfaces, 6,13-bis(triisopropylsilylethynyl)pentacene was printed to fabricate OTFTs and inverters. With the benefit of the PS interlayer, the electrical properties of the OTFTs on a flexible plastic substrate were significantly improved, as shown by a field-effect mobility (μFET) of 0.27 cm2 V-1 s-1 and an on/off current ratio (Ion/Ioff) of greater than 106. In contrast, the untreated systems showed a low μFET of less than 0.02 cm2 V-1 s-1 and Ion/Ioff ∼ 104. Additionally, the all-inkjet-printed inverters based on the PS-modified surfaces exhibited a voltage gain of 7.17 V V-1. The all-organic-based TFTs and inverters, including deformable and transparent PEDOT:PSS electrodes with a sheet resistance of 160-250 Ω sq-1, exhibited a light transmittance of higher than 70% (at wavelength of 550 nm). Specifically, there was no significant degradation in the electrical performance of the interface engineering-assisted system after 1000 bending cycles at a radius of 5 mm.

Fully inkjet-printed short-channel organic thin-film transistors and inverter arrays on flexible substrates

We report fully inkjet-printed organic thin-film transistors (OTFTs) and inverters with an average channel length of 9 μm and minimized overlap capacitance between gate and source/drain (S/D) electrodes on a flexible plastic substrate. Metal-organic precursor-type silver ink, poly(4-vinylphenol), and 6, 13-bis (triisopropylsilylethynyl)pentacene were used to form the gate and S/D electrodes, the gate dielectric, and the active semiconductor layer, respectively. Well-defined S/D electrodes with narrow width and spacing can be realized by introducing a separate printing process and interdigitated structure with a cartridge that can eject a 1 picoliter volume of ink droplets without any assistant surface treatments or structures. Fully inkjet-printed short channel OTFT arrays presenting an average mobility of 0.065 cm2 V−1 s−1 and on/off ratio of 4 × 103 and inverter arrays exhibiting a voltage gain of 5.5 at a V DD of −30 V and good frequency response were demonstrated.

The rapid and dense assembly of solution-processed single-wall carbon nanotube semiconducting films via an acid-based additive in the aqueous dispersion

The rapid and dense assembly of solution-processed single-wall carbon nanotube (SWCNT) semiconducting films is the key enabling factor for their practical applications to large-area electronics and potentially, roll-to-roll based process development. In this study, we demonstrate a significant reduction in the assembly time for a commercial nanotube dispersion (95%-purified semiconducting SWCNT ink), whilst maintaining a high-quality film with better density, by adding a ∼0.1% volume ratio of nitric acid to the dispersion. A rapidly and densely assembled film was formed after deposition for less than 30 seconds, compared to more than several minutes in a commercial reference ink as previously reported by many research groups. The relationships among the zeta potential, pH concentration, and deposition time of the engineered dispersion were also investigated. The electrostatically weakened force of the ionic surfactants in the engineered inks leads to the rapid formation of densely packed SWCNT films, thereby enabling the fabrication of high-performance SWCNT thin film transistors (TFTs) with a field-effect mobility of 18.80 ± 2.08 cm2 V−1 s−1 and on/off ratios of ≥104 in a significantly reduced process time.

Accurate Defect Density-of-State Extraction Based on Back-Channel Surface Potential Measurement for Solution-Processed Metal-Oxide Thin-Film Transistors

We report more accurate extraction method of the defect density of states for solution-processed indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Since the solution-processed IGZO TFTs have a very thin (~8 nm) active semiconductor layer, their back-channel surface potential should be considered in the field-effect method. If the back-channel surface potential is ignored, deviation between theoretically derived and experimentally measured activation energy data becomes more significant as the thickness of the semiconductor layer decreases in comparison with its Debye length. Dependence of the back-channel surface potential on the applied gate voltages was verified by scanning Kelvin probe microscopy and found to be proportional to the gate voltages. The modified field-effect method provided a more accurate model of the activation energy over the subthreshold region and correspondingly more accurate defect density of states of the IGZO TFTs.