Ji-Jan Chen

Unified methodology for heterogeneous integration with CoWoS technology

Interposer has emerged as a promising alternative of multiple-die integration to provide high-bandwidth transmission and smaller power consumption. However, few works study the design methodology to utilize interposer advantages and explore the relationship among different dies. As TSMCs Chip-on-Wafer-on-Substrate (CoWoS™) technology offered as an enabling solution to system integration, this paper presents complete design methodology validated by CoWoS™ to implement an interposer design. Along with the introduced methodology, three critical stages are further discussed: design planning, interposer testing, and RC extraction. With unified bump planning and routing co-design, inter-die wirelength and routability are greatly improved. An efficient testing scheme is introduced to adopt probe-pads for enabling interposer testability, and a general RC extraction modeling is discussed to help commercial tools capture the coupling between metal wires in the interposer. We develop an industrial test chip by the methodology, and the silicon result reveals that our methodology is compatible with commercial tools and achieves high correlation in interposer integration.

Investigation of WLCSP corrosion induced reliability failure on halogens environment for wearable electronics

Continuous miniaturization of microelectronic devices is enabling more portable and wearable electronic products such as thinner smart phones and smart watches. WLCSP (Wafer Level Chip Size Package) has been widely adopted for portable and wearable electronic products due to its compactness. Microelectronic devices in wearable products may be exposed to chlorine and fluorine because they come in direct contact with the human body under wearing condition. Products of chlorine corrosion have been found in WLCSP product evaluations, thus it is necessary to investigate WLCSP corrosion resistance and the factors affecting its corrosion reliability.