Wei-Pin Changchien

Unified methodology for heterogeneous integration with CoWoS technology

Interposer has emerged as a promising alternative of multiple-die integration to provide high-bandwidth transmission and smaller power consumption. However, few works study the design methodology to utilize interposer advantages and explore the relationship among different dies. As TSMCs Chip-on-Wafer-on-Substrate (CoWoS™) technology offered as an enabling solution to system integration, this paper presents complete design methodology validated by CoWoS™ to implement an interposer design. Along with the introduced methodology, three critical stages are further discussed: design planning, interposer testing, and RC extraction. With unified bump planning and routing co-design, inter-die wirelength and routability are greatly improved. An efficient testing scheme is introduced to adopt probe-pads for enabling interposer testability, and a general RC extraction modeling is discussed to help commercial tools capture the coupling between metal wires in the interposer. We develop an industrial test chip by the methodology, and the silicon result reveals that our methodology is compatible with commercial tools and achieves high correlation in interposer integration.

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects

This paper presents a novel diagnosis algorithm for small delay defects (SDD). Faster-than-at-speed test sets are generated by masking long paths in the circuit for testing SDD. The proposed diagnosis technique uses timing upper and lower bound to improve the diagnosis resolution. Also, timing-aware single location at a time (TA-SLAT) technique is proposed to diagnose multiple SDD. Test results of different test speeds, if available, can be combined to further improve the diagnosis results. Experimental results on five advanced industrial designs show the accuracy of the proposed technique.