Ji-Jon Sit

An ultra-low-power programmable analog bionic ear processor

We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-/spl mu/m BiCMOS technology with a power consumption of 211 /spl mu/W and 77-dB dynamic range of operation. The 9.58 mm/spl times/9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 /spl mu/W power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.

A Low-Power Blocking-Capacitor-Free Charge-Balanced Electrode-Stimulator Chip With Less Than 6 nA DC Error for 1-mA Full-Scale Stimulation

Large dc blocking capacitors are a bottleneck in reducing the size and cost of neural implants. We describe an electrode-stimulator chip that removes the need for large dc blocking capacitors in neural implants by achieving precise charge-balanced stimulation with <6 nA of dc error. For cochlear implant patients, this is well below the industrys safety limit of 25 nA. Charge balance is achieved by dynamic current balancing to reduce the mismatch between the positive and negative phases of current to 0.4%, followed by a shorting phase of at least 1 ms between current pulses to further reduce the charge error. On +6 and -9 V rails in a 0.7-mum AMI high voltage process, the power consumption of a single channel of this chip is 47 muW when biasing power is shared by 16 channels.

An analog bionic ear processor with zero-crossing detection

A 75 dB 251 /spl mu/W analog speech processor is described that preserves the performance, robustness, and programmability needed for deaf patients at a reduced power consumption compared to that of implementations with A/D and DSP. It also provides zero-crossing outputs for stimulation strategies that use phase information to improve performance.

A Cochlear-Implant Processor for Encoding Music and Lowering Stimulation Power

Cochlear implants (CIs), or bionic ears, restore hearing in profoundly deaf (greater than -90 dB hearing loss) patients. They function by transforming frequency patterns in sound into corresponding spatial electrode-stimulation patterns for the auditory nerve. Over the past 20 years, improvements in sound-processing strategies, in the number of electrodes and channels, and in the rate of stimulation have yielded improved sentence and word recognition scores in patients. Next- generation implants will be fully implanted inside the patients body. Consequently, power consumption requirements for signal processing will be very stringent.

A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends

We describe a 470 /spl mu/W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51 dB of input dynamic range. The 16 channels were programmed to cover the entire audio frequency spectrum in a logarithmic or mel-scale fashion and sampled at 312.5 Hz with 64 discriminable levels per channel. The processor also includes an on-chip low-power microphone front end that transduces sound to an electrical signal that is input to each of the 16 channels. The processor, implemented in a 1.5 /spl mu/m process on a 9.23 mm/spl times/9.58 mm chip, with a 2.8 V supply, offers an order-of-magnitude power saving over more traditional A-to-D-then-DSP processors implemented in advanced submicron processes. It is thus suited for fully-implanted bionic ear processors of the future or portable speech-recognition front ends.

A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends

Next-generation bionic ears or cochlear implants will be fully implanted inside the body of the patient and consequently have very stringent requirements on the power consumption used for signal processing. We describe a low-power programmable analog VLSI processing channel that implements bandpass filtering, envelope detection, logarithmic mapping and analog-to-digital conversion. A bionic ear processor may be implemented through the use of several such parallel channels. In a proof-of-concept 1.5 /spl mu/m AMI MOSIS implementation, the most power-hungry channel of our system (7.5 kHz center frequency) consumed 7.8 /spl mu/W of power, had an internal dynamic range (IDR) of 51 dB, and provided 64 discriminable levels of loudness per channel. Such numbers already satisfy the requirements of todays commercial bionic ear processors and can lower the power consumption of even advanced DSP processing schemes of the future by an order of magnitude. Our processing channel is also well suited for use in low power speech recognition front ends, which commonly require the same sequence of operations in cepstrum-like front ends. Future improvements in the interfaces between the various stages of our processing channel, which were not optimized in this implementation, promise a potential internal dynamic range of more than 60 dB with little or no increase in power.

Biasing techniques for subthreshold MOS resistive grids

A classic resistive network implemented using MOS transistors suffers from nonlinearity in the subthreshold exponential parameter /spl kappa/ that arises due to varying V/sub GB/ and V/sub BS/. We show two biasing techniques that alleviate these effects. The first technique always uses transistors with constant gate-to-bulk voltage. The second technique uses a novel bulk-to-source biasing scheme to ensure zero bulk-to-source voltage. We propose a PMOS spatial filtering circuit that employs this scheme to extend the range of linearity of subthreshold resistive networks. Measured experimental results from a 1.5um CMOS process show that our spatial filtering circuit has less than 5% variation in space-constant over a measured 94dB (100fA-5nA) dynamic range as opposed to a conventional spatial filtering circuit, which for the same variation has a measured dynamic range of less than 80dB (100fA-1nA). Our techniques should be useful in translinear MOS circuits where linear operation over a wide dynamic range of input currents is important.